The openocd 0.5.0 release.

Remove '-dev' version tag: 0.5.0-dev -> 0.5.0
arm11: disable broken optimization for setting current scan chain
2011-08-09 13:34:50 +08:00 · 2011-08-08 22:33:41 +02:00 · 2011-08-03 17:36:57 +01:00 · 2011-08-02 13:10:03 +01:00 · 2011-08-01 17:16:10 +01:00 · 2011-07-29 17:01:31 +01:00
39 changed files with 1065 additions and 265 deletions
--- a/Makefile.am
+++ b/Makefile.am
@@ -3,7 +3,7 @@
 AUTOMAKE_OPTIONS = gnu 1.6

 # make sure we pass the correct jimtcl flags to distcheck
-DISTCHECK_CONFIGURE_FLAGS = --with-jim-ext=nvp --disable-lineedit
+DISTCHECK_CONFIGURE_FLAGS = --with-jim-ext=nvp --disable-lineedit --disable-install-jim

 nobase_dist_pkgdata_DATA = \
 	contrib/libdcc/dcc_stdio.c \
@@ -68,6 +68,9 @@ TCL_FILES = find $(srcdir)/$(TCL_PATH) -name '*.cfg' -o -name '*.tcl' | \
 		sed -e 's,^$(srcdir)/$(TCL_PATH),,'

 dist-hook:
+	if test -d $(srcdir)/.git -a \( ! -e $(distdir)/ChangeLog -o -w $(distdir)/ChangeLog \) ; then \
+		git --git-dir $(srcdir)/.git log | $(srcdir)/tools/git2cl/git2cl > $(distdir)/ChangeLog ; \
+	fi
 	for i in $$($(TCL_FILES)); do \
 		j="$(distdir)/$(TCL_PATH)/$$i" && \
 		mkdir -p "$$(dirname $$j)" && \
--- a/configure.in
+++ b/configure.in
@@ -1,5 +1,5 @@
 AC_PREREQ(2.60)
-AC_INIT([openocd], [0.5.0-dev],
+AC_INIT([openocd], [0.5.0],
  [OpenOCD Mailing List <openocd-development@lists.berlios.de>])
 AC_CONFIG_SRCDIR([src/openocd.c])

@@ -774,7 +774,7 @@ fi

 if test "$use_internal_jimtcl" = yes; then
  if test -f "$srcdir/jimtcl/configure.ac"; then
-    AX_CONFIG_SUBDIR_OPTION([jimtcl], [--with-jim-ext=nvp --disable-lineedit])
+    AX_CONFIG_SUBDIR_OPTION([jimtcl], [--with-jim-ext=nvp --disable-lineedit --disable-install-jim])
  else
    AC_MSG_ERROR([jimtcl not found, run git submodule init and git submodule update.])
  fi
@@ -873,14 +873,23 @@ if test $build_ft2232_ftd2xx = yes -o $build_presto_ftd2xx = yes ; then
    AC_MSG_ERROR([Option: --with-ftd2xx-linux-tardir appears wrong, cannot find: ${FTD2XX_H}])
    fi
    CFLAGS="$CFLAGS -I$with_ftd2xx_linux_tardir"
-    FTD2XX_LDFLAGS="-L$with_ftd2xx_linux_tardir"
-    FTD2XX_LIB="-lftd2xx"
-    if test $with_ftd2xx_lib != shared; then
-      # Test #1 - Future proof - if/when ftdichip fixes their distro.
-      # Try it with the simple ".a" suffix.
-      FTD2XX_LIB="$with_ftd2xx_linux_tardir/static_lib/libftd2xx.a"
-      if test -f "${FTD2XX_LIB}"; then
-        FTD2XX_LDFLAGS="${FTD2XX_LDFLAGS}/static_lib"
+    if test $with_ftd2xx_lib = shared; then
+       FTD2XX_LDFLAGS="-L$with_ftd2xx_linux_tardir"
+       FTD2XX_LIB="-lftd2xx"
+    else
+      # Test #1 - v1.0.x
+      case "$host_cpu" in
+      i?86|x86_32)
+              dir=build/i386;;
+      amd64|x86_64)
+              dir=build/x86_64;;
+      *)
+              dir=none;;
+      esac
+      if test -f "$with_ftd2xx_linux_tardir/$dir/libftd2xx.a"; then
+          FTD2XX_LDFLAGS="-L$with_ftd2xx_linux_tardir/$dir"
+          # Also needs -lrt
+          FTD2XX_LIB="-lftd2xx -lrt"
      else
        # Test Number2.
        # Grr.. perhaps it exists as a version number?
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -526,7 +526,7 @@ OpenOCD mailing list.
@item @b{Jim vs. Tcl}
@* Jim-Tcl is a stripped down version of the well known Tcl language,
 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
-fewer features. Jim-Tcl is a single .C file and a single .H file and
+fewer features. Jim-Tcl is several dozens of .C files and .H files and
 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
 4.2 MB .zip file containing 1540 files. 

@@ -676,8 +676,6 @@ setting from within a telnet or gdb session using @command{debug_level
 You can redirect all output from the daemon to a file using the
@option{-l <logfile>} switch.

-For details on the @option{-p} option. @xref{Connecting to GDB}.
-
 Note! OpenOCD will launch the GDB & telnet server even if it can not
 establish a connection with the target. In general, it is possible for
 the JTAG controller to be unresponsive until the target is set up
@@ -1279,7 +1277,7 @@ at91sam3u4c.cfg  lm3s9b9x.cfg  samsung_s3c6410.cfg
 at91sam3u4e.cfg  lpc1768.cfg   sharp_lh79532.cfg
 at91sam3uXX.cfg  lpc2103.cfg   smdk6410.cfg
 at91sam7sx.cfg   lpc2124.cfg   smp8634.cfg
-at91sam9260.cfg  lpc2129.cfg   stm32.cfg
+at91sam9260.cfg  lpc2129.cfg   stm32f1x.cfg
 c100.cfg         lpc2148.cfg   str710.cfg
 c100config.tcl   lpc2294.cfg   str730.cfg
 c100helper.tcl   lpc2378.cfg   str750.cfg
@@ -3604,14 +3602,7 @@ At this writing, the supported CPU types and variants are:
 (Support for this is preliminary and incomplete.)
@item @code{cortex_a8} -- this is an ARMv7 core with an MMU
@item @code{cortex_m3} -- this is an ARMv7 core, supporting only the
-compact Thumb2 instruction set.  It supports one variant:
-@itemize @minus
-@item @code{lm3s} ... Use this when debugging older Stellaris LM3S targets.
-This will cause OpenOCD to use a software reset rather than asserting
-SRST, to avoid a issue with clearing the debug registers.
-This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will
-be detected and the normal reset behaviour used.
-@end itemize
+compact Thumb2 instruction set.
@item @code{dragonite} -- resembles arm966e
@item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
 (Support for this is still incomplete.)
@@ -4764,44 +4755,51 @@ applied to all of them.
@end quotation
@end deffn

-@deffn {Flash Driver} stm32x
-All members of the STM32 microcontroller family from ST Microelectronics
+@deffn {Flash Driver} stm32f1x
+All members of the STM32f1x microcontroller family from ST Microelectronics
 include internal flash and use ARM Cortex M3 cores.
 The driver automatically recognizes a number of these chips using
 the chip identification register, and autoconfigures itself.

@example
-flash bank $_FLASHNAME stm32x 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
@end example

-Some stm32x-specific commands
-@footnote{Currently there is a @command{stm32x mass_erase} command.
+Some stm32f1x-specific commands
+@footnote{Currently there is a @command{stm32f1x mass_erase} command.
 That seems pointless since the same effect can be had using the
 standard @command{flash erase_address} command.}
 are defined:

-@deffn Command {stm32x lock} num
+@deffn Command {stm32f1x lock} num
 Locks the entire stm32 device.
 The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn

-@deffn Command {stm32x unlock} num
+@deffn Command {stm32f1x unlock} num
 Unlocks the entire stm32 device.
 The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn

-@deffn Command {stm32x options_read} num
+@deffn Command {stm32f1x options_read} num
 Read and display the stm32 option bytes written by
-the @command{stm32x options_write} command.
+the @command{stm32f1x options_write} command.
 The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn

-@deffn Command {stm32x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
+@deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
 Writes the stm32 option byte with the specified values.
 The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@end deffn

+@deffn {Flash Driver} stm32f2x
+All members of the STM32f2x microcontroller family from ST Microelectronics
+include internal flash and use ARM Cortex M3 cores.
+The driver automatically recognizes a number of these chips using
+the chip identification register, and autoconfigures itself.
+@end deffn
+
@deffn {Flash Driver} str7x
 All members of the STR7 microcontroller family from ST Microelectronics
 include internal flash and use ARM7TDMI cores.
@@ -4884,6 +4882,19 @@ flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
@end example
@end deffn

+@deffn {Flash Driver} fm3
+All members of the FM3 microcontroller family from Fujitsu
+include internal flash and use ARM Cortex M3 cores.
+The @var{fm3} driver uses the @var{target} parameter to select the
+correct bank config, it can currently be one of the following:
+@code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
+@code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
+	
+@example
+flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
+@end example
+@end deffn
+
@subsection str9xpec driver
@cindex str9xpec

--- a/2
+++ b/2
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -45,10 +45,11 @@ libopenocd_la_CPPFLAGS = -DPKGBLDDATE=\"`date +%F-%R`\"
 # guess-rev.sh returns either a repository version ID or "-snapshot"
 if RELEASE
 libopenocd_la_CPPFLAGS += -DRELSTR=\"\"
+libopenocd_la_CPPFLAGS += -DGITVERSION=\"\"
 else
 libopenocd_la_CPPFLAGS += -DRELSTR=\"`$(top_srcdir)/guess-rev.sh $(top_srcdir)`\"
-endif
 libopenocd_la_CPPFLAGS += -DGITVERSION=\"`cd $(top_srcdir) && git describe`\"
+endif

 # add default CPPFLAGS
 libopenocd_la_CPPFLAGS += $(AM_CPPFLAGS) $(CPPFLAGS)
--- a/src/flash/nand/lpc3180.c
+++ b/src/flash/nand/lpc3180.c
@@ -1317,7 +1317,7 @@ COMMAND_HANDLER(handle_lpc3180_select_command)
      if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 	command_print(CMD_CTX, "%s controller selected", selected[lpc3180_info->selected_controller]);
      else{
-            command_print(CMD_CTX, lpc3180_info->is_bulk?"%s controller selected bulk mode is avaliable":"%s controller selected bulk mode is not avaliable", selected[lpc3180_info->selected_controller]);
+            command_print(CMD_CTX, lpc3180_info->is_bulk?"%s controller selected bulk mode is available":"%s controller selected bulk mode is not available", selected[lpc3180_info->selected_controller]);
      }
 

--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -24,13 +24,14 @@ NOR_DRIVERS = \
 	pic32mx.c \
 	stmsmi.c \
 	stellaris.c \
-	stm32x.c \
-	stm32f2xxx.c \
+	stm32f1x.c \
+	stm32f2x.c \
 	str7x.c \
 	str9x.c \
 	str9xpec.c \
 	tms470.c \
-	virtual.c
+	virtual.c \
+	fm3.c

 # Disabled for now, it generates warnings
 # dsp5680xx_flash.c 
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -32,8 +32,8 @@ extern struct flash_driver str9x_flash;
 extern struct flash_driver aduc702x_flash;
 extern struct flash_driver stellaris_flash;
 extern struct flash_driver str9xpec_flash;
-extern struct flash_driver stm32x_flash;
-extern struct flash_driver stm32xf2xxx_flash;
+extern struct flash_driver stm32f1x_flash;
+extern struct flash_driver stm32f2x_flash;
 extern struct flash_driver tms470_flash;
 extern struct flash_driver ecosflash_flash;
 extern struct flash_driver ocl_flash;
@@ -44,6 +44,7 @@ extern struct flash_driver virtual_flash;
 extern struct flash_driver stmsmi_flash;
 extern struct flash_driver em357_flash;
 //extern struct flash_driver dsp5680xx_flash;
+extern struct flash_driver fm3_flash;

 /**
 * The list of built-in flash drivers.
@@ -61,8 +62,8 @@ static struct flash_driver *flash_drivers[] = {
 	&aduc702x_flash,
 	&stellaris_flash,
 	&str9xpec_flash,
-	&stm32x_flash,
-	&stm32xf2xxx_flash,
+	&stm32f1x_flash,
+	&stm32f2x_flash,
 	&tms470_flash,
 	&ecosflash_flash,
 	&ocl_flash,
@@ -74,6 +75,7 @@ static struct flash_driver *flash_drivers[] = {
 	&em357_flash,
 	// Disabled for now, it generates warnings
 	//&dsp5680xx_flash,
+	&fm3_flash,
 	NULL,
 };

--- a/src/flash/nor/fm3.c
+++ b/src/flash/nor/fm3.c
@@ -0,0 +1,654 @@
+/***************************************************************************
+ *   Copyright (C) 2011 by Marc Willam, Holger Wech                        *
+ *   m.willam@gmx.eu                                                       *
+ *   Copyright (C) 2011 Ronny Strutz                                       *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <helper/binarybuffer.h>
+#include <target/algorithm.h>
+#include <target/armv7m.h>
+
+#define FLASH_DQ6 0x00000040	/* Data toggle flag bit (TOGG) position */
+#define FLASH_DQ5 0x00000020	/* Time limit exceeding flag bit (TLOV) position */
+
+enum fm3_variant
+{
+	mb9bfxx1,
+	mb9bfxx2,
+	mb9bfxx3,
+	mb9bfxx4,
+	mb9bfxx5,
+	mb9bfxx6
+};
+
+struct fm3_flash_bank
+{
+	struct working_area *write_algorithm;
+	enum fm3_variant variant;
+	int probed;
+};
+
+FLASH_BANK_COMMAND_HANDLER(fm3_flash_bank_command)
+{
+	struct fm3_flash_bank *fm3_info;
+
+	if (CMD_ARGC < 6)
+	{
+		LOG_WARNING("incomplete flash_bank fm3 configuration");
+		return ERROR_FLASH_BANK_INVALID;
+	}
+
+	LOG_INFO("******HWE* FLASH CMD Parameter %s", CMD_ARGV[5]);
+
+	fm3_info = malloc(sizeof(struct fm3_flash_bank));
+	bank->driver_priv = fm3_info;
+
+	if (strcmp(CMD_ARGV[5], "mb9bfxx1.cpu") == 0)
+	{
+		fm3_info->variant = mb9bfxx1;
+	}
+	else if (strcmp(CMD_ARGV[5], "mb9bfxx2.cpu") == 0)
+	{
+		fm3_info->variant = mb9bfxx2;
+	}
+	else if (strcmp(CMD_ARGV[5], "mb9bfxx3.cpu") == 0)
+	{
+		fm3_info->variant = mb9bfxx3;
+	}
+	else if (strcmp(CMD_ARGV[5], "mb9bfxx4.cpu") == 0)
+	{
+		fm3_info->variant = mb9bfxx4;
+	}
+	else if (strcmp(CMD_ARGV[5], "mb9bfxx5.cpu") == 0)
+	{
+		fm3_info->variant = mb9bfxx5;
+	}
+	else if (strcmp(CMD_ARGV[5], "mb9bfxx6.cpu") == 0)
+	{
+		fm3_info->variant = mb9bfxx6;
+		LOG_INFO("******HWE* fm3 Variant set to: mb9bfxx6");
+	}
+	else
+	{
+		LOG_ERROR("unknown fm3 variant: %s", CMD_ARGV[5]);
+		free(fm3_info);
+		return ERROR_FLASH_BANK_INVALID;
+	}
+
+	fm3_info->write_algorithm = NULL;
+	fm3_info->probed = 0;
+
+	return ERROR_OK;
+}
+
+static int fm3_busy_wait(struct target *target, uint32_t offset, int timeout_ms)
+{
+	int retval = ERROR_OK;
+	uint16_t state1, state2;
+	int ms = 0;
+
+	while(1) {
+		target_read_u16(target, offset, &state1);	/* dummy-read - see flash manual */
+		target_read_u16(target, offset, &state1);
+		target_read_u16(target, offset, &state2);
+
+		if ( (state1 & FLASH_DQ6) == (state2 & FLASH_DQ6) ) {
+			break;
+		}
+		else if (state1 & FLASH_DQ5) {
+			target_read_u16(target, offset, &state1);
+			target_read_u16(target, offset, &state2);
+			if ( (state1 & FLASH_DQ6) != (state2 & FLASH_DQ6) )
+				retval = ERROR_FLASH_OPERATION_FAILED;
+			break;
+		}
+		usleep(1000);
+		++ms;
+
+		if (ms > timeout_ms) {
+			LOG_ERROR("toggle bit reading timed out!");
+			retval = ERROR_FLASH_OPERATION_FAILED;
+			break;
+		}
+	}
+
+	if (retval == ERROR_OK)
+		LOG_DEBUG("fm3_busy_wait(%x) needs about %d ms", offset, ms);
+
+	return retval;
+}
+
+static int fm3_erase(struct flash_bank *bank, int first, int last)
+{
+	struct target *target = bank->target;
+	int retval = ERROR_OK;
+	uint32_t u32DummyRead;
+	int sector, odd;
+
+	if (target->state != TARGET_HALTED) {
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	LOG_INFO("Fujitsu MB9Bxxx: Sector Erase ... (%d to %d)", first, last);
+
+	target_write_u32(target, 0x40000000, 0x0001);		/* FASZR = 0x01, Enables CPU Programming Mode */
+	target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */
+
+	for (sector = first ; sector <= last ; sector++) {
+		uint32_t offset = bank->sectors[sector].offset;
+
+		for (odd = 0; odd < 2 ; odd++) {
+
+			if (odd)
+				offset += 4;
+
+			target_write_u16(target, 0x1550, 0x00AA);
+			target_write_u16(target, 0x0AA8, 0x0055);
+			target_write_u16(target, 0x1550, 0x0080);
+			target_write_u16(target, 0x1550, 0x00AA);
+			target_write_u16(target, 0x0AA8, 0x0055);
+			target_write_u16(target, offset, 0x0030);
+
+			retval = fm3_busy_wait(target, offset, 500);
+
+			if (retval != ERROR_OK)
+				break;
+		}
+		bank->sectors[sector].is_erased = 1;
+	}
+
+	target_write_u32(target, 0x40000000, 0x0002);
+	target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */
+
+	return retval;
+}
+
+static int fm3_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+	struct fm3_flash_bank *fm3_info = bank->driver_priv;
+	struct target *target = bank->target;
+	uint32_t buffer_size = 8192;
+	struct working_area *source;
+	uint32_t address = bank->base + offset;
+	struct reg_param reg_params[4];
+	struct armv7m_algorithm armv7m_info;
+	int retval = ERROR_OK;
+
+	/* RAMCODE used for fm3 Flash programming:                 */
+	/* R0 keeps source start address         (u32Source)       */
+	/* R1 keeps target start address         (u32Target)       */
+	/* R2 keeps number of halfwords to write (u32Count)        */
+	/* R3 returns result value               (u32FlashResult)  */
+
+	const uint8_t fm3_flash_write_code[] = {
+								/*    fm3_FLASH_IF->FASZ &= 0xFFFD;                               */
+	0x00, 0xBF,                 /*        NOP                                                     */
+	0x5F, 0xF0, 0x80, 0x43,     /*        MOVS.W   R3, #(fm3_FLASH_IF->FASZ)                      */
+	0x1B, 0x68,                 /*        LDR      R3, [R3]                                       */
+	0x4F, 0xF6, 0xFD, 0x74,     /*        MOVW     R4, #0xFFFD                                    */
+	0x23, 0x40,                 /*        ANDS     R3, R3, R4                                     */
+	0x5F, 0xF0, 0x80, 0x44,     /*        MOVS.W   R4, #(fm3_FLASH_IF->FASZ)                      */
+	0x23, 0x60,                 /*        STR      R3, [R4]                                       */
+								/*    fm3_FLASH_IF->FASZ |= 1;                                    */
+	0x5F, 0xF0, 0x80, 0x43,     /*        MOVS.W   R3, #(fm3_FLASH_IF->FASZ)                      */
+	0x1B, 0x68,                 /*        LDR      R3, [R3]                                       */
+	0x53, 0xF0, 0x01, 0x03,     /*        ORRS.W   R3, R3, #1                                     */
+	0x5F, 0xF0, 0x80, 0x44,     /*        MOVS.W   R4, #(fm3_FLASH_IF->FASZ)                      */
+	0x23, 0x60,                 /*        STR      R3, [R4]                                       */
+	                            /*    u32DummyRead = fm3_FLASH_IF->FASZ;                          */
+	0x2B, 0x4B,                 /*        LDR.N    R3, ??u32DummyRead                             */
+	0x5F, 0xF0, 0x80, 0x44,     /*        MOVS.W   R4, #(fm3_FLASH_IF->FASZ)                      */
+	0x24, 0x68,                 /*        LDR      R4, [R4]                                       */
+	0x1C, 0x60,                 /*        STR      R4, [R3]                                       */
+	                            /*    u32FlashResult = FLASH_WRITE_NO_RESULT                      */
+	0x2A, 0x4B,                 /*        LDR.N    R3, ??u32FlashResult                           */
+	0x00, 0x24,                 /*        MOVS     R4, #0                                         */
+	0x1C, 0x60,                 /*        STR      R4, [R3]                                       */
+	                            /*    while ((u32Count > 0 ) && (u32FlashResult                   */
+	                            /*      == FLASH_WRITE_NO_RESULT))                                */
+	0x01, 0x2A,                 /* L0:    CMP      R2, #1                                         */
+	0x32, 0xDB,                 /*        BLT.N    L1                                             */
+	0x27, 0x4B,                 /*        LDR.N    R3, ??u32FlashResult                           */
+	0x1B, 0x68,                 /*        LDR      R3, [R3]                                       */
+	0x00, 0x2B,                 /*        CMP      R3, #0                                         */
+	0x2E, 0xD1,                 /*        BNE.N    L1                                             */
+	                            /*    *(FLASH_SEQ_1550) = FLASH_WRITE_1;                          */
+	0x41, 0xF2, 0x50, 0x53,     /*        MOVW     R3, #0x1550                                    */
+	0xAA, 0x24,                 /*        MOVS     R4. #0xAA                                      */
+	0x1C, 0x80,                 /*        STRH     R4, [R3]                                       */
+	                            /*    *(FLASH_SEQ_0AA8) = FLASH_WRITE_2;                          */
+	0x40, 0xF6, 0xA8, 0x23,     /*        MOVW     R3, #0x0AA8                                    */
+	0x55, 0x24,                 /*        MOVS     R4. #0x55                                      */
+	0x1C, 0x80,                 /*        STRH     R4, [R3]                                       */
+	                            /*    *(FLASH_SEQ_1550) = FLASH_WRITE_3;                          */
+	0x41, 0xF2, 0x50, 0x53,     /*        MOVW     R3, #0x1550                                    */
+	0xA0, 0x24,                 /*        MOVS     R4. #0xA0                                      */
+	0x1C, 0x80,                 /*        STRH     R4, [R3]                                       */
+	                            /*    *(volatile uint16_t*)u32Target                              */
+	                            /*      = *(volatile uint16_t*)u32Source;                         */
+	0x03, 0x88,                 /*        LDRH     R3, [R0]                                       */
+	0x0B, 0x80,                 /*        STRH     R3, [R1]                                       */
+	                            /*    while (u32FlashResult == FLASH_WRITE_NO_RESTULT)            */
+	0x1E, 0x4B,                 /* L2:    LDR.N    R3, ??u32FlashResult                           */
+	0x1B, 0x68,                 /*        LDR      R3, [R3]                                       */
+	0x00, 0x2B,                 /*        CMP      R3, #0                                         */
+	0x11, 0xD1,                 /*        BNE.N    L3                                             */
+	                            /*    if ((*(volatile uint16_t*)u32Target & FLASH_DQ5)             */
+	                            /*      == FLASH_DQ5)                                             */
+	0x0B, 0x88,                 /*        LDRH     R3, [R1]                                       */
+	0x9B, 0x06,                 /*        LSLS     R3, R3, #0x1A                                  */
+	0x02, 0xD5,                 /*        BPL.N    L4                                             */
+	                            /*    u32FlashResult = FLASH_WRITE_TIMEOUT                        */
+	0x1B, 0x4B,                 /*        LDR.N    R3, ??u32FlashResult                           */
+	0x02, 0x24,                 /*        MOVS     R4, #2                                         */
+	0x1C, 0x60,                 /*        STR      R4, [R3]                                       */
+	                            /*    if ((*(volatile uint16_t *)u32Target & FLASH_DQ7)            */
+	                            /*      == (*(volatile uint16_t*)u32Source & FLASH_DQ7))          */
+	0x0B, 0x88,                 /* L4:    LDRH     R3, [R1]                                       */
+	0x13, 0xF0, 0x80, 0x03,     /*        ANDS.W   R3, R3, #0x80                                  */
+	0x04, 0x88,                 /*        LDRH     R4, [R0]                                       */
+	0x14, 0xF0, 0x80, 0x04,     /*        ANDS.W   R4, R4, #0x80                                  */
+	0xA3, 0x42,                 /*        CMP      R3, R4                                         */
+	0xED, 0xD1,                 /*        BNE.N    L2                                             */
+	                            /*    u32FlashResult = FLASH_WRITE_OKAY                           */
+	0x15, 0x4B,                 /*        LDR.N    R3, ??u32FlashResult                           */
+	0x01, 0x24,                 /*        MOVS     R4, #1                                         */
+	0x1C, 0x60,                 /*        STR      R4, [R3]                                       */
+	0xE9, 0xE7,                 /*        B.N      L2                                             */
+	                            /*    if (u32FlashResult != FLASH_WRITE_TIMEOUT)                   */
+	0x13, 0x4B,                 /*        LDR.N    R3, ??u32FlashResult                           */
+	0x1B, 0x68,                 /*        LDR      R3, [R3]                                       */
+	0x02, 0x2B,                 /*        CMP      R3, #2                                         */
+	0x02, 0xD0,                 /*        BEQ.N    L5                                             */
+	                            /*    u32FlashResult = FLASH_WRITE_NO_RESULT                      */
+	0x11, 0x4B,                 /*        LDR.N    R3, ??u32FlashResult                           */
+	0x00, 0x24,                 /*        MOVS     R4, #0                                         */
+	0x1C, 0x60,                 /*        STR      R4, [R3]                                       */
+	                            /*    u32Count--;                                                 */
+	0x52, 0x1E,                 /* L5:    SUBS     R2, R2, #1                                     */
+	                            /*    u32Source += 2;                                             */
+	0x80, 0x1C,                 /*        ADDS     R0, R0, #2                                     */
+	                            /*    u32Target += 2;                                             */
+	0x89, 0x1C,                 /*        ADDS     R1, R1, #2                                     */
+	0xCA, 0xE7,                 /*        B.N      L0                                             */
+	                            /*    fm3_FLASH_IF->FASZ &= 0xFFFE;                               */
+	0x5F, 0xF0, 0x80, 0x43,     /* L1:    MOVS.W   R3, #(fm3_FLASH_IF->FASZ)                      */
+	0x1B, 0x68,                 /*        LDR      R3, [R3]                                       */
+	0x4F, 0xF6, 0xFE, 0x74,     /*        MOVW     R4, #0xFFFE                                    */
+	0x23, 0x40,                 /*        ANDS     R3, R3, R4                                     */
+	0x5F, 0xF0, 0x80, 0x44,     /*        MOVS.W   R4, #(fm3_FLASH_IF->FASZ)                      */
+	0x23, 0x60,                 /*        STR      R3, [R4]                                       */
+	                            /*    fm3_FLASH_IF->FASZ |= 2;                                    */
+	0x5F, 0xF0, 0x80, 0x43,     /*        MOVS.W   R3, #(fm3_FLASH_IF->FASZ)                      */
+	0x1B, 0x68,                 /*        LDR      R3, [R3]                                       */
+	0x53, 0xF0, 0x02, 0x03,     /*        ORRS.W   R3, R3, #2                                     */
+	0x5F, 0xF0, 0x80, 0x44,     /*        MOVS.W   R4, #(fm3_FLASH_IF->FASZ)                      */
+	0x23, 0x60,                 /*        STR      R4, [R3]                                       */
+	                            /*    u32DummyRead = fm3_FLASH_IF->FASZ;                          */
+	0x04, 0x4B,                 /*        LDR.N    R3, ??u32DummyRead                             */
+	0x5F, 0xF0, 0x80, 0x44,     /*        MOVS.W   R4, #(fm3_FLASH_IF->FASZ)                      */
+	0x24, 0x68,                 /*        LDR      R4, [R4]                                       */
+	0x1C, 0x60,                 /*        STR      R4, [R3]                                       */
+	                            /*    copy u32FlashResult to R3 for return value                  */
+	0xDF, 0xF8, 0x0C, 0x30,     /*        LDR.W    R3, ??u32FlashResult                           */
+	0x1B, 0x68,                 /*        LDR      R3, [R3]                                       */
+	                            /*    Breakpoint here                                             */
+	0x00, 0xBE,                 /* Breakpoint #0                                                  */
+	0x00, 0x00,                 /*    alignment padding bytes                                     */
+	0x00, 0x80, 0xFF, 0x1F,     /* u32DummyRead address in RAM (0x1FFF8000)                       */
+	0x04, 0x80, 0xFF, 0x1F      /* u32FlashResult address in RAM (0x1FFF8004)                     */
+	};
+
+	LOG_INFO("Fujitsu MB9B500: FLASH Write ...");
+
+	/* disable HW watchdog */
+	target_write_u32(target, 0x40011C00, 0x1ACCE551);
+	target_write_u32(target, 0x40011C00, 0xE5331AAE);
+	target_write_u32(target, 0x40011008, 0x00000000);
+
+	count = count / 2;		/* number bytes -> number halfwords */
+
+	/* check code alignment */
+	if (offset & 0x1)
+	{
+		LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
+		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+	}
+
+	/* allocate working area with flash programming code */
+	if (target_alloc_working_area(target, sizeof(fm3_flash_write_code),
+			&fm3_info->write_algorithm) != ERROR_OK)
+	{
+		LOG_WARNING("no working area available, can't do block memory writes");
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+
+	retval = target_write_buffer(target, fm3_info->write_algorithm->address,
+		sizeof(fm3_flash_write_code), fm3_flash_write_code);
+	if (retval != ERROR_OK)
+		return retval;
+
+	/* memory buffer */
+	while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
+	{
+		buffer_size /= 2;
+		if (buffer_size <= 256)
+		{
+			/* free working area, if write algorithm already allocated */
+			if (fm3_info->write_algorithm)
+			{
+				target_free_working_area(target, fm3_info->write_algorithm);
+			}
+
+			LOG_WARNING("no large enough working area available, can't do block memory writes");
+			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		}
+	}
+
+	armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+	armv7m_info.core_mode = ARMV7M_MODE_ANY;
+
+	init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); // source start address
+	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); // target start address
+	init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); // number of halfwords to program
+	init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);  // result
+
+	/* write code buffer and use Flash programming code within fm3           */
+	/* Set breakpoint to 0 with time-out of 1000 ms                          */
+	while (count > 0)
+	{
+		uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
+
+		/* for some reason the first 8 byte of code are corrupt when target_run_algorithm() returns */
+		/* need some more investigation on this                                                     */
+		retval = target_write_buffer(target,
+				fm3_info->write_algorithm->address, 8, fm3_flash_write_code);
+		if (retval != ERROR_OK)
+			return retval;
+
+
+		retval = target_write_buffer(target,
+				source->address, thisrun_count * 2, buffer);
+		if (retval != ERROR_OK)
+			break;
+
+		buf_set_u32(reg_params[0].value, 0, 32, source->address);
+		buf_set_u32(reg_params[1].value, 0, 32, address);
+		buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
+
+
+		retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
+				fm3_info->write_algorithm->address, 0, 1000, &armv7m_info);
+		if (retval != ERROR_OK)
+		{
+			LOG_ERROR("error executing fm3 Flash programming algorithm");
+			retval = ERROR_FLASH_OPERATION_FAILED;
+			break;
+		}
+
+#if 0
+		/* debug the corrupted 8 bytes */
+		unsigned char buf[256];
+		retval = target_read_buffer(target, fm3_info->write_algorithm->address, 256, buf);
+		if (retval != ERROR_OK)
+			printf("cannot read buffer\n");
+		unsigned int i;
+		for ( i = 0; i < sizeof(fm3_flash_write_code); i++)
+			if (buf[i] != fm3_flash_write_code[i])
+				printf("broken: %d %02x != %02x\n", i, buf[i], fm3_flash_write_code[i]);
+#endif
+
+		if (buf_get_u32(reg_params[3].value, 0, 32) != ERROR_OK)
+		{
+			LOG_ERROR("Fujitsu MB9B500: FLASH programming ERROR (Timeout) -> Reg R3: %x",
+					buf_get_u32(reg_params[3].value, 0, 32));
+			retval = ERROR_FLASH_OPERATION_FAILED;
+			break;
+		}
+
+		buffer  += thisrun_count * 2;
+		address += thisrun_count * 2;
+		count   -= thisrun_count;
+	}
+
+	target_free_working_area(target, source);
+	target_free_working_area(target, fm3_info->write_algorithm);
+
+	destroy_reg_param(&reg_params[0]);
+	destroy_reg_param(&reg_params[1]);
+	destroy_reg_param(&reg_params[2]);
+	destroy_reg_param(&reg_params[3]);
+
+	return retval;
+}
+
+static int fm3_probe(struct flash_bank *bank)
+{
+	struct fm3_flash_bank *fm3_info = bank->driver_priv;
+	uint16_t num_pages;
+
+	if (bank->target->state != TARGET_HALTED)
+	{
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	num_pages = 6;				/* max number of Flash pages for malloc */
+	fm3_info->probed = 0;
+
+	bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
+	bank->base = 0x00000000;
+	num_pages = 2;				/* start with smallest Flash pages number */
+	bank->size = 32 * 1024;		/* bytes */
+
+	bank->sectors[0].offset = 0;
+	bank->sectors[0].size = 16 * 1024;
+	bank->sectors[0].is_erased = -1;
+	bank->sectors[0].is_protected = -1;
+
+	bank->sectors[1].offset = 0x4000;
+	bank->sectors[1].size = 16 * 1024;
+	bank->sectors[1].is_erased = -1;
+	bank->sectors[1].is_protected = -1;
+
+	if (fm3_info->variant == mb9bfxx1)
+	{
+		num_pages = 3;
+		bank->size = 64 * 1024; /* bytes */
+		bank->num_sectors = num_pages;
+
+		bank->sectors[2].offset = 0x8000;
+		bank->sectors[2].size = 32 * 1024;
+		bank->sectors[2].is_erased = -1;
+		bank->sectors[2].is_protected = -1;
+	}
+
+	if (  (fm3_info->variant == mb9bfxx2)
+		|| (fm3_info->variant == mb9bfxx4)
+		|| (fm3_info->variant == mb9bfxx5)
+		|| (fm3_info->variant == mb9bfxx6))
+	{
+		num_pages = 3;
+		bank->size = 128 * 1024; // bytes
+		bank->num_sectors = num_pages;
+
+		bank->sectors[2].offset = 0x8000;
+		bank->sectors[2].size = 96 * 1024;
+		bank->sectors[2].is_erased = -1;
+		bank->sectors[2].is_protected = -1;
+	}
+
+	if ( (fm3_info->variant == mb9bfxx4)
+		|| (fm3_info->variant == mb9bfxx5)
+		|| (fm3_info->variant == mb9bfxx6))
+	{
+		num_pages = 4;
+		bank->size = 256 * 1024; // bytes
+		bank->num_sectors = num_pages;
+
+		bank->sectors[3].offset = 0x20000;
+		bank->sectors[3].size = 128 * 1024;
+		bank->sectors[3].is_erased = -1;
+		bank->sectors[3].is_protected = -1;
+	}
+
+	if ( (fm3_info->variant == mb9bfxx5)
+		|| (fm3_info->variant == mb9bfxx6))
+	{
+		num_pages = 5;
+		bank->size = 384 * 1024; // bytes
+		bank->num_sectors = num_pages;
+
+		bank->sectors[4].offset = 0x40000;
+		bank->sectors[4].size = 128 * 1024;
+		bank->sectors[4].is_erased = -1;
+		bank->sectors[4].is_protected = -1;
+	}
+
+	if (fm3_info->variant == mb9bfxx6)
+	{
+		num_pages = 6;
+		bank->size = 512 * 1024; // bytes
+		bank->num_sectors = num_pages;
+
+		bank->sectors[5].offset = 0x60000;
+		bank->sectors[5].size = 128 * 1024;
+		bank->sectors[5].is_erased = -1;
+		bank->sectors[5].is_protected = -1;
+	}
+
+	fm3_info->probed = 1;
+
+	return ERROR_OK;
+}
+
+static int fm3_auto_probe(struct flash_bank *bank)
+{
+	struct fm3_flash_bank *fm3_info = bank->driver_priv;
+	if (fm3_info->probed)
+		return ERROR_OK;
+	return fm3_probe(bank);
+}
+
+static int fm3_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+	snprintf(buf, buf_size, "Fujitsu fm3 Device does not support Chip-ID (Type unknown)");
+	return ERROR_OK;
+}
+
+static int fm3_chip_erase(struct flash_bank *bank)
+{
+	struct target *target = bank->target;
+	int retval = ERROR_OK;
+	uint32_t u32DummyRead;
+
+	if (target->state != TARGET_HALTED)
+	{
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	LOG_INFO("Fujitsu MB9Bxxx: Chip Erase ... (may take several seconds)");
+
+	/* Implement Flash chip erase (mass erase) completely on host */
+	target_write_u32(target, 0x40000000, 0x0001);		/* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash access) */
+	target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */
+
+	target_write_u16(target, 0x00001550, 0x00AA); 		/* Flash unlock sequence */
+	target_write_u16(target, 0x00000AA8, 0x0055);
+	target_write_u16(target, 0x00001550, 0x0080);
+	target_write_u16(target, 0x00001550, 0x00AA);
+	target_write_u16(target, 0x00000AA8, 0x0055);
+	target_write_u16(target, 0x00001550, 0x0010); 		/* Chip Erase command */
+
+	retval = fm3_busy_wait(target, 0xAA8, 20000);
+
+	target_write_u32(target, 0x40000000, 0x0002);
+	target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */
+
+	return retval;
+}
+
+COMMAND_HANDLER(fm3_handle_chip_erase_command)
+{
+	int i;
+
+	if (CMD_ARGC < 1)
+	{
+		command_print(CMD_CTX, "fm3 chip_erase <bank>");
+		return ERROR_OK;
+	}
+
+	struct flash_bank *bank;
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+	if (ERROR_OK != retval)
+		return retval;
+
+	if (fm3_chip_erase(bank) == ERROR_OK)
+	{
+		/* set all sectors as erased */
+		for (i = 0; i < bank->num_sectors; i++)
+			bank->sectors[i].is_erased = 1;
+
+		command_print(CMD_CTX, "fm3 chip erase complete");
+	}
+	else
+	{
+		command_print(CMD_CTX, "fm3 chip erase failed");
+	}
+
+	return ERROR_OK;
+}
+
+static const struct command_registration fm3_exec_command_handlers[] = {
+	{
+		.name = "chip_erase",
+		.handler = fm3_handle_chip_erase_command,
+		.mode = COMMAND_EXEC,
+		.usage = "bank_id",
+		.help = "Erase entire Flash device.",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration fm3_command_handlers[] = {
+	{
+		.name = "fm3",
+		.mode = COMMAND_ANY,
+		.help = "fm3 Flash command group",
+		.chain = fm3_exec_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+struct flash_driver fm3_flash = {
+	.name = "fm3",
+	.commands = fm3_command_handlers,
+	.flash_bank_command = fm3_flash_bank_command,
+	.erase = fm3_erase,
+	.write = fm3_write_block,
+	.probe = fm3_probe,
+	.auto_probe = fm3_auto_probe,
+	.erase_check = default_flash_mem_blank_check,
+	.info = fm3_info,
+};
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -783,7 +783,7 @@ static int stellaris_protect(struct flash_bank *bank, int set, int first, int la

 	if (!set)
 	{
-		LOG_ERROR("Hardware doesn't suppport page-level unprotect. "
+		LOG_ERROR("Hardware doesn't support page-level unprotect. "
 			"Try the 'recover' command.");
 		return ERROR_INVALID_ARGUMENTS;
 	}
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -1544,16 +1544,16 @@ static const struct command_registration stm32x_exec_command_handlers[] = {

 static const struct command_registration stm32x_command_handlers[] = {
 	{
-		.name = "stm32x",
+		.name = "stm32f1x",
 		.mode = COMMAND_ANY,
-		.help = "stm32x flash command group",
+		.help = "stm32f1x flash command group",
 		.chain = stm32x_exec_command_handlers,
 	},
 	COMMAND_REGISTRATION_DONE
 };

-struct flash_driver stm32x_flash = {
-	.name = "stm32x",
+struct flash_driver stm32f1x_flash = {
+	.name = "stm32f1x",
 	.commands = stm32x_command_handlers,
 	.flash_bank_command = stm32x_flash_bank_command,
 	.erase = stm32x_erase,
--- a/src/flash/nor/stm32f2xxx.c
+++ b/src/flash/nor/stm32f2xxx.c
@@ -48,8 +48,7 @@
 *
 */

-
-/* Danger!!!! The STM32F1xxxx and STM32F2xxxx series actually have
+/* Danger!!!! The STM32F1x and STM32F2x series actually have
 * quite different flash controllers.
 *
 * What's more scary is that the names of the registers and their
@@ -57,7 +56,7 @@
 * can be very different.
 *
 * To reduce testing complexity and dangers of regressions,
- * a seperate file is used for stm32fx2222.
+ * a seperate file is used for stm32fx2x.
 *
 * 1mByte part with 4 x 16, 1 x 64, 7 x 128kBytes sectors
 *
@@ -73,16 +72,16 @@
 * PM0059
 * www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/CD00233952.pdf
 *
- * STM32F1xxx series - notice that this code was copy, pasted and knocked
- * into a stm32f2xxx driver, so in case something has been converted or
+ * STM32F1x series - notice that this code was copy, pasted and knocked
+ * into a stm32f2x driver, so in case something has been converted or
 * bugs haven't been fixed, here are the original manuals:
 *
 * RM0008 - Reference manual
 *
 * RM0042, the Flash programming manual for low-, medium- high-density and
- * connectivity line STM32F10xxx devices
+ * connectivity line STM32F10x devices
 *
- * PM0068, the Flash programming manual for XL-density STM32F10xxx devices.
+ * PM0068, the Flash programming manual for XL-density STM32F10x devices.
 *
 */

@@ -683,16 +682,16 @@ static const struct command_registration stm32x_exec_command_handlers[] = {

 static const struct command_registration stm32x_command_handlers[] = {
 	{
-		.name = "stm32f2xxx",
+		.name = "stm32f2x",
 		.mode = COMMAND_ANY,
-		.help = "stm32f2xxx flash command group",
+		.help = "stm32f2x flash command group",
 		.chain = stm32x_exec_command_handlers,
 	},
 	COMMAND_REGISTRATION_DONE
 };

-struct flash_driver stm32xf2xxx_flash = {
-	.name = "stm32f2xxx",
+struct flash_driver stm32f2x_flash = {
+	.name = "stm32f2x",
 	.commands = stm32x_command_handlers,
 	.flash_bank_command = stm32x_flash_bank_command,
 	.erase = stm32x_erase,
--- a/src/flash/startup.tcl
+++ b/src/flash/startup.tcl
@@ -1,2 +1,13 @@
 # Defines basic Tcl procs for OpenOCD flash module

+# ease migration to updated flash driver
+proc stm32x args {
+	echo "DEPRECATED! use 'stm32f1x $args' not 'stm32x $args'"
+	eval stm32f1x $args
+}
+
+proc stm32f2xxx args {
+	echo "DEPRECATED! use 'stm32f2x $args' not 'stm32f2xxx $args'"
+	eval stm32f2x $args
+}
+
--- a/src/jtag/drivers/ft2232.c
+++ b/src/jtag/drivers/ft2232.c
@@ -515,7 +515,7 @@ static int ft2232_write(uint8_t* buf, int size, uint32_t* bytes_written)
 	if ((status = FT_Write(ftdih, buf, size, &dw_bytes_written)) != FT_OK)
 	{
 		*bytes_written = dw_bytes_written;
-		LOG_ERROR("FT_Write returned: %lu", status);
+		LOG_ERROR("FT_Write returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 	else
@@ -558,7 +558,7 @@ static int ft2232_read(uint8_t* buf, uint32_t size, uint32_t* bytes_read)
 					  *bytes_read, &dw_bytes_read)) != FT_OK)
 		{
 			*bytes_read = 0;
-			LOG_ERROR("FT_Read returned: %lu", status);
+			LOG_ERROR("FT_Read returned: %" PRIu32, status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
 		*bytes_read += dw_bytes_read;
@@ -2215,11 +2215,11 @@ static int ft2232_init_ftd2xx(uint16_t vid, uint16_t pid, int more, int* try_mor

 		if (more)
 		{
-			LOG_WARNING("unable to open ftdi device (trying more): %lu", status);
+			LOG_WARNING("unable to open ftdi device (trying more): %" PRIu32, status);
 			*try_more = 1;
 			return ERROR_JTAG_INIT_FAILED;
 		}
-		LOG_ERROR("unable to open ftdi device: %lu", status);
+		LOG_ERROR("unable to open ftdi device: %" PRIu32, status);
 		status = FT_ListDevices(&num_devices, NULL, FT_LIST_NUMBER_ONLY);
 		if (status == FT_OK)
 		{
@@ -2235,7 +2235,7 @@ static int ft2232_init_ftd2xx(uint16_t vid, uint16_t pid, int more, int* try_mor

 			if (status == FT_OK)
 			{
-				LOG_ERROR("ListDevices: %lu", num_devices);
+				LOG_ERROR("ListDevices: %" PRIu32, num_devices);
 				for (i = 0; i < num_devices; i++)
 					LOG_ERROR("%" PRIu32 ": \"%s\"", i, desc_array[i]);
 			}
@@ -2254,14 +2254,26 @@ static int ft2232_init_ftd2xx(uint16_t vid, uint16_t pid, int more, int* try_mor

 	if ((status = FT_SetLatencyTimer(ftdih, ft2232_latency)) != FT_OK)
 	{
-		LOG_ERROR("unable to set latency timer: %lu", status);
+		LOG_ERROR("unable to set latency timer: %" PRIu32, status);
 		return ERROR_JTAG_INIT_FAILED;
 	}

 	if ((status = FT_GetLatencyTimer(ftdih, &latency_timer)) != FT_OK)
 	{
-		LOG_ERROR("unable to get latency timer: %lu", status);
-		return ERROR_JTAG_INIT_FAILED;
+		/* ftd2xx 1.04 (linux) has a bug when calling FT_GetLatencyTimer
+		 * so ignore errors if using this driver version */
+		DWORD dw_version;
+		
+		status = FT_GetDriverVersion(ftdih, &dw_version);
+		LOG_ERROR("unable to get latency timer: %" PRIu32, status);
+		
+		if ((status == FT_OK) && (dw_version == 0x10004)) {
+			LOG_ERROR("ftd2xx 1.04 detected - this has known issues " \
+					"with FT_GetLatencyTimer, upgrade to a newer version");
+		}
+		else {
+			return ERROR_JTAG_INIT_FAILED;
+		}
 	}
 	else
 	{
@@ -2270,19 +2282,19 @@ static int ft2232_init_ftd2xx(uint16_t vid, uint16_t pid, int more, int* try_mor

 	if ((status = FT_SetTimeouts(ftdih, 5000, 5000)) != FT_OK)
 	{
-		LOG_ERROR("unable to set timeouts: %lu", status);
+		LOG_ERROR("unable to set timeouts: %" PRIu32, status);
 		return ERROR_JTAG_INIT_FAILED;
 	}

 	if ((status = FT_SetBitMode(ftdih, 0x0b, 2)) != FT_OK)
 	{
-		LOG_ERROR("unable to enable bit i/o mode: %lu", status);
+		LOG_ERROR("unable to enable bit i/o mode: %" PRIu32, status);
 		return ERROR_JTAG_INIT_FAILED;
 	}

 	if ((status = FT_GetDeviceInfo(ftdih, &ftdi_device, &deviceID, SerialNumber, Description, NULL)) != FT_OK)
 	{
-		LOG_ERROR("unable to get FT_GetDeviceInfo: %lu", status);
+		LOG_ERROR("unable to get FT_GetDeviceInfo: %" PRIu32, status);
 		return ERROR_JTAG_INIT_FAILED;
 	}
 	else
@@ -2292,8 +2304,8 @@ static int ft2232_init_ftd2xx(uint16_t vid, uint16_t pid, int more, int* try_mor
 		unsigned no_of_known_types = ARRAY_SIZE(type_str) - 1;
 		unsigned type_index = ((unsigned)ftdi_device <= no_of_known_types)
 			? ftdi_device : FT_DEVICE_UNKNOWN;
-		LOG_INFO("device: %lu \"%s\"", ftdi_device, type_str[type_index]);
-		LOG_INFO("deviceID: %lu", deviceID);
+		LOG_INFO("device: %" PRIu32 " \"%s\"", ftdi_device, type_str[type_index]);
+		LOG_INFO("deviceID: %" PRIu32, deviceID);
 		LOG_INFO("SerialNumber: %s", SerialNumber);
 		LOG_INFO("Description: %s", Description);
 	}
@@ -2307,7 +2319,7 @@ static int ft2232_purge_ftd2xx(void)

 	if ((status = FT_Purge(ftdih, FT_PURGE_RX | FT_PURGE_TX)) != FT_OK)
 	{
-		LOG_ERROR("error purging ftd2xx device: %lu", status);
+		LOG_ERROR("error purging ftd2xx device: %" PRIu32, status);
 		return ERROR_JTAG_INIT_FAILED;
 	}

@@ -3628,7 +3640,7 @@ static int signalyzer_h_led_set(unsigned char channel, unsigned char led,
 	if ((status = signalyzer_h_ctrl_write(SIGNALYZER_DATA_BUFFER_ADDR,
 			((uint32_t)(channel << 8) | led))) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write  returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write  returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

@@ -3636,7 +3648,7 @@ static int signalyzer_h_led_set(unsigned char channel, unsigned char led,
 			(SIGNALYZER_DATA_BUFFER_ADDR + 1),
 			((uint32_t)(on_time << 8) | off_time))) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write  returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write  returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

@@ -3644,14 +3656,14 @@ static int signalyzer_h_led_set(unsigned char channel, unsigned char led,
 			(SIGNALYZER_DATA_BUFFER_ADDR + 2),
 			((uint32_t)cycles))) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write  returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write  returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

 	if ((status = signalyzer_h_ctrl_write(SIGNALYZER_COMMAND_ADDR,
 			SIGNALYZER_COMMAND_LED_SET)) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write  returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write  returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

@@ -3740,7 +3752,7 @@ static int signalyzer_h_init(void)
 	if ((status = signalyzer_h_ctrl_write(SIGNALYZER_COMMAND_ADDR,
 			SIGNALYZER_COMMAND_VERSION)) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

@@ -3750,7 +3762,7 @@ static int signalyzer_h_init(void)
 			(SIGNALYZER_DATA_BUFFER_ADDR + i),
 			&read_buf[i])) != FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_read returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_read returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -3764,21 +3776,21 @@ static int signalyzer_h_init(void)
 	if ((status = signalyzer_h_ctrl_write(SIGNALYZER_DATA_BUFFER_ADDR,
 			(uint32_t)(signalyzer_h_side << 8))) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

 	if ((status = signalyzer_h_ctrl_write(SIGNALYZER_DATA_BUFFER_ADDR + 1,
 			0x0404)) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

 	if ((status = signalyzer_h_ctrl_write(SIGNALYZER_COMMAND_ADDR,
 			SIGNALYZER_COMMAND_GPIO_STATE)) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

@@ -3786,28 +3798,28 @@ static int signalyzer_h_init(void)
 	if ((status = signalyzer_h_ctrl_write(SIGNALYZER_DATA_BUFFER_ADDR,
 			((uint32_t)(signalyzer_h_side << 8) | 0x01))) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

 	if ((status = signalyzer_h_ctrl_write(
 			(SIGNALYZER_DATA_BUFFER_ADDR + 1), 0xA000)) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

 	if ((status = signalyzer_h_ctrl_write(
 			(SIGNALYZER_DATA_BUFFER_ADDR + 2), 0x0008)) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

 	if ((status = signalyzer_h_ctrl_write(SIGNALYZER_COMMAND_ADDR,
 			SIGNALYZER_COMMAND_I2C)) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_write returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

@@ -3816,7 +3828,7 @@ static int signalyzer_h_init(void)
 	if ((status = signalyzer_h_ctrl_read(SIGNALYZER_COMMAND_ADDR,
 			&read_buf[0])) != FT_OK)
 	{
-		LOG_ERROR("signalyzer_h_ctrl_read returned: %lu", status);
+		LOG_ERROR("signalyzer_h_ctrl_read returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}

@@ -3830,7 +3842,7 @@ static int signalyzer_h_init(void)
 					(SIGNALYZER_DATA_BUFFER_ADDR + i),
 					&read_buf[i])) != FT_OK)
 			{
-				LOG_ERROR("signalyzer_h_ctrl_read returned: %lu",
+				LOG_ERROR("signalyzer_h_ctrl_read returned: %" PRIu32,
 					status);
 				return ERROR_JTAG_DEVICE_ERROR;
 			}
@@ -3895,7 +3907,7 @@ static int signalyzer_h_init(void)
 				((uint32_t)(signalyzer_h_side << 8) | 0x01)))
 			!= FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 				status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -3903,7 +3915,7 @@ static int signalyzer_h_init(void)
 		if ((status = signalyzer_h_ctrl_write(SIGNALYZER_COMMAND_ADDR,
 				SIGNALYZER_COMMAND_POWERCONTROL_SET)) != FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -3913,7 +3925,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_DATA_BUFFER_ADDR,
 				(uint32_t)(signalyzer_h_side << 8))) != FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -3922,7 +3934,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_DATA_BUFFER_ADDR + 1, 0x0000))
 			!= FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -3930,7 +3942,7 @@ static int signalyzer_h_init(void)
 		if ((status = signalyzer_h_ctrl_write(SIGNALYZER_COMMAND_ADDR,
 				SIGNALYZER_COMMAND_GPIO_MODE)) != FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -3940,7 +3952,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_DATA_BUFFER_ADDR,
 				(uint32_t)(signalyzer_h_side << 8))) != FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -3949,7 +3961,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_DATA_BUFFER_ADDR + 1, 0x4040))
 			!= FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -3958,7 +3970,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_COMMAND_ADDR,
 				SIGNALYZER_COMMAND_GPIO_STATE)) != FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -4030,7 +4042,7 @@ static int signalyzer_h_init(void)
 				((uint32_t)(signalyzer_h_side << 8) | 0x01)))
 			!= FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -4039,7 +4051,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_COMMAND_ADDR,
 				SIGNALYZER_COMMAND_POWERCONTROL_SET)) != FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -4051,7 +4063,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_DATA_BUFFER_ADDR,
 				(uint32_t)(signalyzer_h_side << 8))) != FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -4060,7 +4072,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_DATA_BUFFER_ADDR + 1, 0x0060))
 			!= FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -4069,7 +4081,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_COMMAND_ADDR,
 				SIGNALYZER_COMMAND_GPIO_MODE)) != FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -4081,7 +4093,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_DATA_BUFFER_ADDR,
 				(uint32_t)(signalyzer_h_side << 8))) != FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -4090,7 +4102,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_DATA_BUFFER_ADDR + 1, 0x0000))
 			!= FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
@@ -4099,7 +4111,7 @@ static int signalyzer_h_init(void)
 				SIGNALYZER_COMMAND_ADDR,
 				SIGNALYZER_COMMAND_GPIO_STATE)) != FT_OK)
 		{
-			LOG_ERROR("signalyzer_h_ctrl_write returned: %lu",
+			LOG_ERROR("signalyzer_h_ctrl_write returned: %" PRIu32,
 					status);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
--- a/src/jtag/drivers/usb_blaster.c
+++ b/src/jtag/drivers/usb_blaster.c
@@ -135,7 +135,7 @@ static int usb_blaster_buf_write(
 	if (status != FT_OK)
 	{
 		*bytes_written = dw_bytes_written;
-		LOG_ERROR("FT_Write returned: %lu", status);
+		LOG_ERROR("FT_Write returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 	*bytes_written = dw_bytes_written;
@@ -168,11 +168,11 @@ usb_blaster_buf_read(uint8_t *buf, unsigned size, uint32_t *bytes_read)
 	if (status != FT_OK)
 	{
 		*bytes_read = dw_bytes_read;
-		LOG_ERROR("FT_Read returned: %lu", status);
+		LOG_ERROR("FT_Read returned: %" PRIu32, status);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 #ifdef _DEBUG_JTAG_IO_
-	LOG_DEBUG("usb_blaster_buf_read %02X (%lu)", buf[0], dw_bytes_read);
+	LOG_DEBUG("usb_blaster_buf_read %02X (%" PRIu32 ")", buf[0], dw_bytes_read);
 #endif
 	*bytes_read = dw_bytes_read;
 	return ERROR_OK;
@@ -384,7 +384,7 @@ static int usb_blaster_init(void)
 	{
 		DWORD num_devices;

-		LOG_ERROR("unable to open ftdi device: %lu", status);
+		LOG_ERROR("unable to open ftdi device: %" PRIu32, status);
 		status = FT_ListDevices(&num_devices, NULL,
 				FT_LIST_NUMBER_ONLY);
 		if (status == FT_OK)
@@ -402,7 +402,7 @@ static int usb_blaster_init(void)

 			if (status == FT_OK)
 			{
-				LOG_ERROR("ListDevices: %lu", num_devices);
+				LOG_ERROR("ListDevices: %" PRIu32, num_devices);
 				for (i = 0; i < num_devices; i++)
 					LOG_ERROR("%i: %s", i, desc_array[i]);
 			}
@@ -421,14 +421,14 @@ static int usb_blaster_init(void)
 	status = FT_SetLatencyTimer(ftdih, 2);
 	if (status != FT_OK)
 	{
-		LOG_ERROR("unable to set latency timer: %lu", status);
+		LOG_ERROR("unable to set latency timer: %" PRIu32, status);
 		return ERROR_JTAG_INIT_FAILED;
 	}

 	status = FT_GetLatencyTimer(ftdih, &latency_timer);
 	if (status != FT_OK)
 	{
-		LOG_ERROR("unable to get latency timer: %lu", status);
+		LOG_ERROR("unable to get latency timer: %" PRIu32, status);
 		return ERROR_JTAG_INIT_FAILED;
 	}
 	LOG_DEBUG("current latency timer: %i", latency_timer);
@@ -436,7 +436,7 @@ static int usb_blaster_init(void)
 	status = FT_SetBitMode(ftdih, 0x00, 0);
 	if (status != FT_OK)
 	{
-		LOG_ERROR("unable to disable bit i/o mode: %lu", status);
+		LOG_ERROR("unable to disable bit i/o mode: %" PRIu32, status);
 		return ERROR_JTAG_INIT_FAILED;
 	}
 #elif BUILD_USB_BLASTER_LIBFTDI == 1
--- a/src/rtos/FreeRTOS.c
+++ b/src/rtos/FreeRTOS.c
@@ -472,7 +472,7 @@ static int FreeRTOS_create( struct target* target )
 	}
 	if ( i >= FREERTOS_NUM_PARAMS )
 	{
-		LOG_OUTPUT("Could not find target in FreeRTOS compatability list\r\n");
+		LOG_OUTPUT("Could not find target in FreeRTOS compatibility list\r\n");
 		return -1;
 	}

--- a/src/rtos/ThreadX.c
+++ b/src/rtos/ThreadX.c
@@ -525,7 +525,7 @@ static int ThreadX_create( struct target* target )
 	}
 	if ( i >= THREADX_NUM_PARAMS )
 	{
-		LOG_OUTPUT("Could not find target in ThreadX compatability list\r\n");
+		LOG_OUTPUT("Could not find target in ThreadX compatibility list\r\n");
 		return -1;
 	}

--- a/src/rtos/eCos.c
+++ b/src/rtos/eCos.c
@@ -416,7 +416,7 @@ static int eCos_create( struct target* target )
 	}
 	if ( i >= ECOS_NUM_PARAMS )
 	{
-		LOG_OUTPUT("Could not find target in eCos compatability list\r\n");
+		LOG_OUTPUT("Could not find target in eCos compatibility list\r\n");
 		return -1;
 	}

--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -199,11 +199,17 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
 	 * NOTE:  the ITRSEL instruction fakes SCREG changing;
 	 * but leaves its actual value unchanged.
 	 */
+#if 0
+	// FIX!!! the optimization below is broken because we do not
+	// invalidate the cur_scan_chain upon a TRST/TMS. See arm_jtag.c
+	// for example on how to invalidate cur_scan_chain. Tested patches gladly
+	// accepted!
 	if (arm11->jtag_info.cur_scan_chain == chain) {
 		JTAG_DEBUG("SCREG <= %d SKIPPED", chain);
 		return jtag_add_statemove((state == ARM11_TAP_DEFAULT)
 					? TAP_DRPAUSE : state);
 	}
+#endif
 	JTAG_DEBUG("SCREG <= %d", chain);

 	arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -392,6 +392,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre
 			{
 				return retval;
 			}
+			current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
 			if (current_instr == arm7_9->thumb_bkpt)
 				if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 				{
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -304,20 +304,32 @@ static int etb_write_reg(struct reg *reg, uint32_t value)
 {
 	struct etb_reg *etb_reg = reg->arch_info;
 	uint8_t reg_addr = etb_reg->addr & 0x7f;
+	struct scan_field fields[3];

 	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);

 	etb_scann(etb_reg->etb, 0x0);
 	etb_set_instr(etb_reg->etb, 0xc);

+	fields[0].num_bits = 32;
 	uint8_t temp0[4];
+	fields[0].out_value = temp0;
 	buf_set_u32(&temp0, 0, 32, value);
+	fields[0].in_value = NULL;

+	fields[1].num_bits = 7;
 	uint8_t temp1;
+	fields[1].out_value = &temp1;
 	buf_set_u32(&temp1, 0, 7, reg_addr);
+	fields[1].in_value = NULL;

+	fields[2].num_bits = 1;
 	uint8_t temp2;
+	fields[2].out_value = &temp2;
 	buf_set_u32(&temp2, 0, 1, 1);
+	fields[2].in_value = NULL;
+
+	jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE);

 	return ERROR_OK;
 }
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -643,7 +643,7 @@ static int mips_m4k_unset_breakpoint(struct target *target,
 			{
 				return retval;
 			}
-
+			current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
 			if (current_instr == MIPS16_SDBBP)
 			{
 				if ((retval = target_write_memory(target, breakpoint->address, 2, 1,
--- a/src/target/smp.c
+++ b/src/target/smp.c
@@ -79,7 +79,7 @@ int gdb_read_smp_packet(struct connection *connection,
 				hex_buffer[2 * i + 1] = DIGITS[t & 0xf];
 			}

-			gdb_put_packet(connection, hex_buffer, len * 2);
+			retval = gdb_put_packet(connection, hex_buffer, len * 2);

 			free(hex_buffer);
 		}
@@ -95,6 +95,7 @@ int gdb_write_smp_packet(struct connection *connection,
 {
 	char *separator;
 	int coreid = 0;
+	int retval = ERROR_OK;

 	/* skip command character */
 	if (target->smp)
@@ -104,13 +105,13 @@ int gdb_write_smp_packet(struct connection *connection,
 			packet+=2;
 			coreid = strtoul(packet, &separator, 16);
 			target->gdb_service->core[1] = coreid;
-			gdb_put_packet(connection, "OK", 2);
+			retval = gdb_put_packet(connection, "OK", 2);
 		}
 	}
 	else
 	{
-		gdb_put_packet(connection,"E01",3);
+		retval = gdb_put_packet(connection,"E01",3);
 	}

-	return ERROR_OK;
+	return retval;
 }
--- a/tcl/board/hitex_stm32-performancestick.cfg
+++ b/tcl/board/hitex_stm32-performancestick.cfg
@@ -5,7 +5,7 @@ reset_config trst_and_srst
 source [find interface/stm32-stick.cfg]

 set  CHIPNAME stm32_hitex
-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]

 # configure str750 connected to jtag chain
 # FIXME -- source [find target/str750.cfg] after cleaning that up
--- a/tcl/board/olimex_stm32_h103.cfg
+++ b/tcl/board/olimex_stm32_h103.cfg
@@ -4,4 +4,4 @@
 # Work-area size (RAM size) = 20kB for STM32F103RB device
 set WORKAREASIZE 0x5000

-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
--- a/tcl/board/olimex_stm32_h107.cfg
+++ b/tcl/board/olimex_stm32_h107.cfg
@@ -5,4 +5,4 @@
 # Work-area size (RAM size) = 64kB for STM32F107VC device
 set WORKAREASIZE 0x10000

-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
--- a/tcl/board/stm32100b_eval.cfg
+++ b/tcl/board/stm32100b_eval.cfg
@@ -4,4 +4,4 @@
 # The chip has only 8KB sram
 set WORKAREASIZE 0x2000

-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
--- a/tcl/board/stm3210b_eval.cfg
+++ b/tcl/board/stm3210b_eval.cfg
@@ -4,4 +4,4 @@
 # increase working area to 32KB for faster flash programming
 set WORKAREASIZE 0x8000

-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
--- a/tcl/board/stm3210c_eval.cfg
+++ b/tcl/board/stm3210c_eval.cfg
@@ -4,4 +4,4 @@
 # increase working area to 32KB for faster flash programming
 set WORKAREASIZE 0x8000

-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
--- a/tcl/board/stm3210e_eval.cfg
+++ b/tcl/board/stm3210e_eval.cfg
@@ -4,7 +4,7 @@
 # increase working area to 32KB for faster flash programming
 set WORKAREASIZE 0x8000

-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]

 #
 # configure FSMC Bank 1 (NOR/PSRAM Bank 2) NOR flash
--- a/tcl/board/stm3220g_eval.cfg
+++ b/tcl/board/stm3220g_eval.cfg
@@ -8,4 +8,4 @@ set WORKAREASIZE 0x20000
 # chip name
 set CHIPNAME STM32F207IGT6

-source [find target/stm32f2xxx.cfg]
+source [find target/stm32f2x.cfg]
--- a/tcl/target/fm3.cfg
+++ b/tcl/target/fm3.cfg
@@ -0,0 +1,47 @@
+# MB96F506
+# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME mb9bf500
+}
+
+if { [info exists ENDIAN] } {
+	set  _ENDIAN $ENDIAN
+} else {
+	set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+# delays on reset lines
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+# Fujitsu cortex-M3 reset configuration
+reset_config trst_only
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# MB9BF506 has 64kB of SRAM on its main system bus 
+$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
+
+# MB9BF506 has 512kB internal FLASH 
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
+
+# 4MHz / 6 = 666kHz, so use 500
+adapter_khz 500
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -1,5 +1,17 @@
 # TI/Luminary Stellaris LM3S chip family

+# Some devices have errata in returning their device class.
+# DEVICECLASS is provided as a manual override
+# Manual setting of a device class of 0xff is not allowed
+
+global _DEVICECLASS
+
+if { [info exists DEVICECLASS ] } {
+   set _DEVICECLASS $DEVICECLASS
+} else {
+   set _DEVICECLASS 0xff
+}
+
 # Luminary chips support both JTAG and SWD transports.
 # Adapt based on what transport is active.
 source [find target/swj-dp.tcl]
@@ -74,7 +86,14 @@ $_TARGETNAME configure -event reset-start {
 	#	/openocd-development/2008-August/003065.html
 	#

-	set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
+	global _DEVICECLASS
+
+	if {$_DEVICECLASS != 0xff} {
+	   set device_class $_DEVICECLASS
+	} else {
+	   set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
+	}
+
 	if {$device_class == 0 || $device_class == 1 || $device_class == 3} {
 		# Sandstorm, Fury and DustDevil are able to use NVIC SYSRESETREQ
 		cortex_m3 reset_config sysresetreq
--- a/tcl/target/stm32.cfg
+++ b/tcl/target/stm32.cfg
@@ -1,75 +1,3 @@
-# script for stm32
-
-if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
-} else {
-   set  _CHIPNAME stm32
-}
-
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
-   set  _WORKAREASIZE $WORKAREASIZE
-} else {
-   set  _WORKAREASIZE 0x4000
-}
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-  # See STM Document RM0008
-  # Section 26.6.3
-   set _CPUTAPID 0x3ba00477
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
-   # FIXME this never gets used to override defaults...
-   set _BSTAPID $BSTAPID
-} else {
-  # See STM Document RM0008
-  # Section 29.6.2
-  # Low density devices, Rev A
-  set _BSTAPID1 0x06412041
-  # Medium density devices, Rev A
-  set _BSTAPID2 0x06410041
-  # Medium density devices, Rev B and Rev Z
-  set _BSTAPID3 0x16410041
-  set _BSTAPID4 0x06420041
-  # High density devices, Rev A
-  set _BSTAPID5 0x06414041
-  # Connectivity line devices, Rev A and Rev Z
-  set _BSTAPID6 0x06418041
-  # XL line devices, Rev A
-  set _BSTAPID7 0x06430041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
-	-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
-	-expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
-	-expected-id $_BSTAPID6 -expected-id $_BSTAPID7
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# flash size will be probed
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32x 0x08000000 0 0 0 $_TARGETNAME
-
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m3 reset_config sysresetreq
+# deprecated cfg file
+echo "DEPRECATED! use script 'target/stm32f1x.cfg' not 'target/stm32.cfg'"
+source [find target/stm32f1x.cfg]
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -0,0 +1,75 @@
+# script for stm32
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME stm32
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set  _WORKAREASIZE $WORKAREASIZE
+} else {
+   set  _WORKAREASIZE 0x4000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0008
+  # Section 26.6.3
+   set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+   # FIXME this never gets used to override defaults...
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0008
+  # Section 29.6.2
+  # Low density devices, Rev A
+  set _BSTAPID1 0x06412041
+  # Medium density devices, Rev A
+  set _BSTAPID2 0x06410041
+  # Medium density devices, Rev B and Rev Z
+  set _BSTAPID3 0x16410041
+  set _BSTAPID4 0x06420041
+  # High density devices, Rev A
+  set _BSTAPID5 0x06414041
+  # Connectivity line devices, Rev A and Rev Z
+  set _BSTAPID6 0x06418041
+  # XL line devices, Rev A
+  set _BSTAPID7 0x06430041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+	-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+	-expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
+	-expected-id $_BSTAPID6 -expected-id $_BSTAPID7
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -0,0 +1,61 @@
+# script for stm32f2xxx
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME stm32f2xxx
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set  _WORKAREASIZE $WORKAREASIZE
+} else {
+   set  _WORKAREASIZE 0x10000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+jtag_khz 1000
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0033
+  # Section 32.6.3 - corresponds to Cortex-M3 r2p0
+   set _CPUTAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0033
+  # Section 32.6.2
+  # 
+  set _BSTAPID 0x06411041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+
--- a/tcl/target/stm32f2xxx.cfg
+++ b/tcl/target/stm32f2xxx.cfg
@@ -1,56 +1,3 @@
-# script for stm32f2xxx
-
-if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
-} else {
-   set  _CHIPNAME stm32f2xxx
-}
-
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 64kB
-if { [info exists WORKAREASIZE] } {
-   set  _WORKAREASIZE $WORKAREASIZE
-} else {
-   set  _WORKAREASIZE 0x10000
-}
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-jtag_khz 1000
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-  # See STM Document RM0033
-  # Section 32.6.3 - corresponds to Cortex-M3 r2p0
-   set _CPUTAPID 0x4ba00477
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
-   set _BSTAPID $BSTAPID
-} else {
-  # See STM Document RM0033
-  # Section 32.6.2
-  # 
-  set _BSTAPID 0x06411041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32f2xxx 0 0 0 0 $_TARGETNAME
-
+# deprecated cfg file
+echo "DEPRECATED! use script 'target/stm32f2x.cfg' not 'target/stm32f2xxx.cfg'"
+source [find target/stm32f2x.cfg]
--- a/tcl/target/stm32xl.cfg
+++ b/tcl/target/stm32xl.cfg
@@ -1,6 +1,6 @@
 # script for stm32xl family (dual flash bank)
-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]

 # flash size will be probed
 set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME stm32x 0x08080000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
--- a/tcl/target/tmpa900.cfg
+++ b/tcl/target/tmpa900.cfg
@@ -1,11 +1,11 @@
 ######################################
-# Target:    Toshiba TMPA910
+# Target:    Toshiba TMPA900
 ######################################

 if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME tmpa910
+   set  _CHIPNAME tmpa900
 }

 if { [info exists ENDIAN] } {
@@ -21,7 +21,7 @@ if { [info exists CPUTAPID ] } {
   set _CPUTAPID 0x07926031
 }

-#TMPA910 has following IDs:
+#TMPA900 has following IDs:
 # CP15.0 register 0x41069265
 # CP15.1 register 0x1d152152
 # ARM core 0x07926031
Author	SHA1	Message	Date
Jean-Christophe PLAGNIOL-VILLARD	2fced63147	The openocd 0.5.0 release. Remove '-dev' version tag: 0.5.0-dev -> 0.5.0	2011-08-09 13:34:50 +08:00
Øyvind Harboe	bbd84417f6	arm11: disable broken optimization for setting current scan chain	2011-08-08 22:33:41 +02:00
Luca Bruno	0d7a948c8d	Automatically generate ChangeLog from git log for release tarball make dist should use git2cl to generate ChangeLog from git history, populating the placeholder file in released tarball. Signed-off-by: Luca Bruno <lucab@debian.org> Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-08-03 17:36:57 +01:00
B. A. Bryce	29f0ac0efd	cfg: allow stellaris device class override Some devices, eg. The Tempest class return the wrong device class when queried. Add the ability to manually override the device class. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-08-02 13:10:03 +01:00
Jie Zhang	d02dfff48b	etb: fix incorrect previous patchset This corrects two issues found with openocd. `d7f71e7fe9` removed some code that was being used. The above then caused even more code to get removed by commit `1cfb2287a6`. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-08-01 17:16:10 +01:00
Spencer Oliver	69ac20a155	cfg: support calling legacy stm32 scripts For the time being we support the old stm32 script names - this will be removed before the next release cycle. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-29 17:01:31 +01:00
Spencer Oliver	633b1a2b49	docs: remove obsolete luminary target info The lm3s variant is not required as this is handled in the target script - see tcl/target/stellaris.cfg. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-28 16:06:24 +01:00
Spencer Oliver	852289bc49	flash: add support for deprecated stm32 flash cmds Issue warning when the old cmd is used and redirect to new supported one. These deprecated cmds will be removed at some point. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-28 12:47:49 +01:00
Spencer Oliver	89f593d8cb	cfg: update scripts to use new stm32 driver names Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-28 11:45:09 +01:00
Spencer Oliver	c73342fbe7	docs: update to use new stm32 driver names Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-28 11:44:48 +01:00
Spencer Oliver	b066a7db24	flash: update stm32 driver names Use consistent names for the stm32 family flash drivers, eg. stm32x -> stm32f1x stm32f2xxx -> stm32f2x this makes it easier to add support for newer stm32 families. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-28 11:42:27 +01:00
Spencer Oliver	b5a324e63c	cfg: add Fujitsu FM3 config Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-27 10:56:25 +01:00
Spencer Oliver	1cfd3fdda9	doc: add Fujitsu FM3 flash driver info Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-27 10:28:24 +01:00
Jie Zhang	ba4b8af4d7	remove doc on the deprecated '-p' option Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-26 21:24:08 +01:00
Jie Zhang	577c3bc087	Update doc about Jim since it's not a single .C file and a single .H file any more Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-26 21:23:20 +01:00
Ronny Strutz	e872d2880e	add Fujitsu FM3 Family flash support Signed-off-by: Ronny Strutz <ronny@ewoks.de> Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-26 21:15:34 +01:00
Michael Hunold	d6c42bf312	CPU name in TMPA900 config file should obviously be TMPA900 (not TMPA910). Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-18 14:24:05 +01:00
Spencer Oliver	ffbb5cd85c	build: do not install jimtcl We now make use of the new jimtcl --disable-install-jim Now we can install openocd without jimtcl bring installed. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-18 14:02:31 +01:00
Spencer Oliver	5e7c8d074c	jimtcl: update to support --disable-install-jim Update jimtcl version to commit 6233a6c5d39928f1bfafa8f41cb1ddf0c5a83de0 This enable to to build jimtcl as a submodule but not install it. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-18 14:01:05 +01:00
Øyvind Harboe	e7269e32a7	stm32f2xxx: comments about frequency choice	2011-07-15 12:05:46 +02:00
Luca Bruno	f44bde23b9	Do not append git info to version string when building from released tarball When building official releases from tarball, git commit info is not available in the building environment. Thus, automake should not try to append the git commit to the version string. Signed-off-by: Luca Bruno <lucab@debian.org> Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-14 10:19:18 +01:00
Spencer Oliver	0ea76bc778	ftd2xx: handle FT_GetLatencyTimer bug in v1.04 Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-12 15:51:18 +01:00
Spencer Oliver	b765688be6	busblaster: Fix warnings when building against D2XX The default is -Werror, so warnings become errors. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-12 14:40:19 +01:00
Steve Bennett	b238735f89	ft2232: Fix warnings when building against D2XX The default is -Werror, so warnings become errors Signed-off-by: Steve Bennett <steveb@workware.net.au> Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-12 12:58:28 +01:00
Steve Bennett	107ddb38b7	ftdi: update for latest libftdi 1.0.4 For libftd2xx1.0.4, which uses a different directory structure than libftd2xx0.4.16 Without this fix the build fails with version 1.0.4 of the driver. Note that this does not fix --with-ftd2xx-lib=shared Signed-off-by: Steve Bennett <steveb@workware.net.au> Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>	2011-07-12 12:35:28 +01:00
Luca Bruno	898dd3af46	Fix typo in command output Fix a bunch of minor typo in user facing output. Signed-off-by: Luca Bruno <lucab@debian.org>	2011-07-10 17:00:57 +02:00
Drasko DRASKOVIC	ac43d7a69f	mips_m4k and arm7_9 : Fix soft bkpt endianess for 16-bit instructions The patch fix comparison of target data on the host by using target_buffer_get_u16() to transform current_instr to _host_ endianess before comparison.	2011-07-04 18:15:18 +02:00