# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2023 HPMicro

adapter speed 10000
source [find interface/hpmicro/hpmicro_evk.cfg]
source [find target/hpmicro/hpm6880.cfg]
# openocd flash driver argument:
#   - option0:
#       [31:28] Flash probe type
#         0 - SFDP SDR / 1 - SFDP DDR
#         2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
#         4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
#         6 - OctaBus DDR (SPI -> OPI DDR)
#         8 - Xccela DDR (SPI -> OPI DDR)
#         10 - EcoXiP DDR (SPI -> OPI DDR)
#       [27:24] Command Pads after Power-on Reset
#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
#       [23:20] Command Pads after Configuring FLASH
#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
#       [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
#         0 - Not needed
#         1 - QE bit is at bit6 in Status Register 1
#         2 - QE bit is at bit1 in Status Register 2
#         3 - QE bit is at bit7 in Status Register 2
#         4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
#       [15:8] Dummy cycles
#         0 - Auto-probed / detected / default value
#         Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
#       [7:4] Misc.
#         0 - Not used
#         1 - SPI mode
#         2 - Internal loopback
#         3 - External DQS
#       [3:0] Frequency option
#         1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
#   - option1:
#       [31:20]  Reserved
#       [19:16] IO voltage
#         0 - 3V / 1 - 1.8V
#       [15:12] Pin group
#         0 - 1st group / 1 - 2nd group
#       [11:8] Connection selection
#         0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
#       [7:0] Drive Strength
#         0 - Default value

# xpi0 configs
#   - flash driver:     hpm_xpi
#   - flash ctrl index: 0xF3000000
#   - base address:     0x80000000
#   - flash size:       0x2000000
#   - flash option0:    0x7
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3000000 0x7

proc init_clock {} {
	mww 0xF4000800 0xFFFFFFFF
	mww 0xF4000810 0xFFFFFFFF
	mww 0xF4000820 0xFFFFFFFF
	mww 0xF4000830 0xFFFFFFFF
	echo "clocks has been enabled!"
}

proc init_ddr3 {} {
# ddr dcdc setup
	mww 0xF4104080 0x10578

# ddr3 setup
	mww 0xF40C0180 0x30000019
	mww 0xF400180C 0x09100401
	mww 0xF4153000 0xF0000010
	mww 0xF30101B0 0
	mww 0xF4150040 0xf004641f
	mww 0xF4153000 0xf0000011
	mww 0xF3013000 0xf4000000
	mww 0xF3010490 1
	mww 0xF3010000 0x1040001
	mww 0xF30100D0 0x4002004e
	mww 0xF3010110 0x05010407
	mww 0xF3010190 0x07040102
	mww 0xF3010194 0x20404
	mww 0xF30101A4 0x20008
	mww 0xF3010240 0x06000600
	mww 0xF3010200 0x1F1F1F
	mww 0xF3010204 0x121212
	mww 0xF3010208 0
	mww 0xF301020C 0
	mww 0xF3010210 0x1F1F
	mww 0xF3010214 0x06030303
	mww 0xF3010218 0x0F060606
	mww 0xF3013000 0xFC000000
	mww 0xF4150054 0xc70
	mww 0xF4150058 0x6
	mww 0xF415005c 0x18
	mww 0xF4150048 0x919c8866
	mww 0xF415004c 0x1a838360
	mww 0xF415008c 0xf06d50
	mww 0xF4150050 0x3002d200
	mww 0xF30101b0 1
	sleep 100
	mww 0xF4150068 0x930035C7
	mww 0xF4150004 0xFF81
	sleep 200
	echo "ddr3 has been enabled!"
}

proc init_dram {} {
# ddr dcdc setup
	mww 0xF4104080 0x10708

# pll1 setup
	mww 0xF40c0180 0xb0000016
	mww 0xF40c0184 0
	mww 0xF40c0188 0xe4e1c00

#ddr setup
	mww 0xF3010000 0x3040000
	mww 0xF30101B0 0
	mww 0xF4150044 0x40a
	mww 0xF4150040 0xf004641f
	mww 0xF4153000 0xf0000011
	mww 0xF3013000 0xf4000000
	mww 0xF3010490 1
	mww 0xF3010000 0x1040000
	mww 0xF3010190 0x07010101
	mww 0xF3010194 0x20404
	mww 0xF30101A4 0x20008
	mww 0xF3010240 0x6000600
	mww 0xF3010200 0x1f1f1f
	mww 0xF3010204 0x70707
	mww 0xF3010208 0
	mww 0xF301020c 0
	mww 0xF3010210 0x1f1f
	mww 0xF3010214 0x6060606
	mww 0xF3010218 0xf0f0606
	mww 0xF3013000 0xfc000000
	mww 0xF4150020 0x3000100
	mww 0xF4150028 0x18002356
	mww 0xF415002c 0x0aac4156
	mww 0xF4150054 0xe73
	mww 0xF4150058 0x5
	mww 0xF415005c 0
	mww 0xF4150048 0xf2adfe53
	mww 0xF415004c 0x22820362
	mww 0xF4150050 0x30020100
	mww 0xF415008c 0xf06d50
	mww 0xF30101b0 1
	sleep 100
	mww 0xF4150068 0x91003587
	mww 0xF4150004 0xF501
	sleep 200
	echo "ddr has been enabled!"
}

$_TARGET0 configure -event reset-init {
	init_clock
	init_ddr3
}