# SPDX-License-Identifier: GPL-2.0-or-later
# Maxim Integrated max32xxx OpenOCD driver configuration file.
# Contains common settings for max32xxx devices.

source [find mem_helper.tcl]
source [find target/swj-dp.tcl]

# Set the adapter speed
if { [info exists ADAPTER_KHZ] } {
   set _ADAPTER_KHZ $ADAPTER_KHZ
} else {
   set _ADAPTER_KHZ 2000
}
adapter speed $_ADAPTER_KHZ

# Target configuration
if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME max32xxx
}

# Add reserved TAP
if { [using_jtag] && [info exists RSV_TAP] } {
   jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version
   jtag newtap rsvtap tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
} else {
   swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version
}


dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_CHIPNAME.cpu cortex_m -dap $_CHIPNAME.dap

# Enable thread-aware debugging
$_CHIPNAME.cpu configure -rtos hwthread

# Setup working area
if { [info exists WORK_START] } {
   set _WORK_START $WORK_START
} else {
   set _WORK_START 0x20005000
}

if { [info exists WORK_SIZE] } {
   set _WORK_SIZE $WORK_SIZE
} else {
   set _WORK_SIZE 0x8000
}

$_CHIPNAME.cpu configure -work-area-phys $_WORK_START -work-area-size $_WORK_SIZE

# Configure flash driver
if { [info exists FLASH_BASE] } {
   set _FLASH_BASE $FLASH_BASE
} else {
   set _FLASH_BASE 0x10000000
}

if { [info exists FLASH_SIZE] } {
   set _FLASH_SIZE $FLASH_SIZE
} else {
   set _FLASH_SIZE 0x10000
}

if { [info exists FLC_BASE] } {
   set _FLC_BASE $FLC_BASE
} else {
   set _FLC_BASE 0x40029000
}

if { [info exists FLASH_SECTOR] } {
   set _FLASH_SECTOR $FLASH_SECTOR
} else {
   set _FLASH_SECTOR 0x2000
}

if { [info exists FLASH_CLK] } {
   set _FLASH_CLK $FLASH_CLK
} else {
   set _FLASH_CLK 96
}

# OPTIONS_128                     0x01 /* Perform 128 bit flash writes */
# OPTIONS_ENC                     0x02 /* Encrypt the flash contents */
# OPTIONS_AUTH                    0x04 /* Authenticate the flash contents */
# OPTIONS_COUNT                   0x08 /* Add counter values to authentication */
# OPTIONS_INTER                   0x10 /* Interleave the authentication and count values*/
# OPTIONS_RELATIVE_XOR            0x20 /* Only XOR the offset of the address when encrypting */
# OPTIONS_KEYSIZE                 0x40 /* Use a 256 bit KEY */

if { [info exists FLASH_OPTIONS] } {
   set _FLASH_OPTIONS $FLASH_OPTIONS
} else {
   set _FLASH_OPTIONS 0
}

flash bank $_CHIPNAME.flash max32xxx $_FLASH_BASE $_FLASH_SIZE 0 0 $_CHIPNAME.cpu \
$_FLC_BASE $_FLASH_SECTOR $_FLASH_CLK $_FLASH_OPTIONS

# call allow_low_pwr_dbg to set this to 1
set ALLOW_LOW_PWR_DBG 0

proc allow_low_pwr_dbg {} {
   global ALLOW_LOW_PWR_DBG

   # set our low-power debug flag
   set ALLOW_LOW_PWR_DBG 1
}

# enable debug in case of low-power mode
proc enable_debug {} {
   set DBGKEY 0xA05F0000
   set C_DEBUGEN 0x00000001
   set C_HALT 0x00000002

   echo "Enable debug to connect in low-power mode"

   # enable debug
   mww 0xE000EDF0 [expr {$DBGKEY | $C_HALT | $C_DEBUGEN}]

   # allow for time waking up
   sleep 500
}

$_CHIPNAME.cpu configure -event reset-deassert-post {
   global ALLOW_LOW_PWR_DBG

   if { $ALLOW_LOW_PWR_DBG == 1 } {
      enable_debug
   }
}