forked from auracaster/openocd
c7073853eb
We want to keep the tri-state buffers located between the FPGA and the board, in 'Z' state until we launch an i2c connection. We launch an i2c start condition, make the SCL direction 'OUT' to start the i2c protocol and at the end of the i2c connection at the stop condition, we re-make the tri-state buffers at 'Z' state. Change-Id: Ic597a70d0427832547f6b539864c24ce20a18c64 Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7989 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
145 lines
2.4 KiB
C
145 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/****************************************************************************
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File : i2c.cpp *
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Contents : i2c bit-bang library *
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Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS. *
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<aboudjelida@nanoxplore.com> *
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<ahmederrachedbjld@gmail.com> *
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*****************************************************************************/
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#include "i2c.h"
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#include "io.h"
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#include "delay.h"
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#include "reg_ezusb.h"
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void start_cd(void)
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{
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PIN_SCL_DIR = 0;
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PIN_SDA_DIR = 0;
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delay_us(10);
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PIN_SDA = 0; //SDA = 1;
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delay_us(1);
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PIN_SCL = 0; //SCL = 1;
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delay_us(1);
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}
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void repeated_start(void)
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{
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PIN_SDA = 1;
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delay_us(1);
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PIN_SCL = 1;
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delay_us(1);
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PIN_SDA = 0;
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delay_us(1);
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PIN_SCL = 0;
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delay_us(1);
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}
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void stop_cd(void)
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{
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PIN_SDA = 0;
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delay_us(1);
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PIN_SCL = 1;
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delay_us(1);
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PIN_SDA = 1;
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delay_us(1);
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PIN_SDA_DIR = 1;
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delay_us(1);
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PIN_SCL_DIR = 1;
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delay_us(1);
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}
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void clock_cd(void)
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{
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PIN_SCL = 1;
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delay_us(1);
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PIN_SCL = 0;
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delay_us(1);
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}
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void send_ack(void)
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{
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PIN_SDA = 0;
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delay_us(1);
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PIN_SCL = 1;
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delay_us(1);
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PIN_SCL = 0;
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delay_us(1);
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}
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void send_nack(void)
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{
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PIN_SDA = 1;
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delay_us(1);
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PIN_SCL = 1;
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delay_us(1);
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PIN_SCL = 0;
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delay_us(1);
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}
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bool get_ack(void)
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{
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PIN_SDA_DIR = 1;
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delay_us(1);
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OED = 0xFE;
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PIN_SCL = 1;
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delay_us(1);
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bool ack = PIN_SDA;
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PIN_SCL = 0;
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delay_us(1);
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OED = 0xFF;
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PIN_SDA_DIR = 0;
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delay_us(1);
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return ack;
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}
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/* here address(8 bits) = adr (7 bits) + type (1 bit) */
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uint8_t get_address(uint8_t adr, uint8_t rdwr)
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{
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adr &= 0x7F;
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adr = adr << 1;
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adr |= (rdwr & 0x01);
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return adr;
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}
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/* here send bit after bit and clocking scl with each bit */
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void send_byte(uint8_t input)
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{
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for (uint8_t i = 0; i < 8; i++) {
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if ((input & 0x80)) {
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PIN_SDA = 1;
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delay_us(1);
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clock_cd();
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} else {
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PIN_SDA = 0;
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delay_us(1);
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clock_cd();
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}
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input = input << 1;
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}
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}
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/* here receive bit after bit and clocking scl with each bit */
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uint8_t receive_byte(void)
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{
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PIN_SDA_DIR = 1; //FX2 <-- FPGA
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OED = 0xFE;
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uint8_t input = 0x00;
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for (uint8_t i = 0; i < 8; i++) {
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PIN_SCL = 1;
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delay_us(1);
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input = input << 1;
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if (PIN_SDA == 1)
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input |= 0x01;
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else
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input |= 0X00;
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PIN_SCL = 0;
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delay_us(1);
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}
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OED = 0xFF;
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PIN_SDA_DIR = 0;
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return input;
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}
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