forked from auracaster/openocd
f906c65fed
The SAP in LS102x SoC's from Freescale is able to read and write to all physical memory locations, independently of CPU cores and DAP. This implementation is 100% based on reverse-engineering of JTAG communication with an LS1021A SAP using a JTAG debugger with SAP support. And as such, this code is for now "works-for-me", pending verification by other OpenOCD users, or even better, actual information from Freescale on the SAP interface. Change-Id: Ibb30945e017894da5c402f9f633fc513bed4e68c Signed-off-by: Esben Haabendal <esben@haabendal.dk> Reviewed-on: http://openocd.zylin.com/3096 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
214 lines
3.2 KiB
Makefile
214 lines
3.2 KiB
Makefile
include $(top_srcdir)/common.mk
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if OOCD_TRACE
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OOCD_TRACE_FILES = oocd_trace.c
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else
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OOCD_TRACE_FILES =
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endif
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SUBDIRS = openrisc
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libtarget_la_LIBADD = $(top_builddir)/src/target/openrisc/libopenrisc.la
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BIN2C = $(top_srcdir)/src/helper/bin2char.sh
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DEBUG_HANDLER = $(srcdir)/xscale/debug_handler.bin
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EXTRA_DIST = \
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startup.tcl \
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$(wildcard $(srcdir)/xscale/*)
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DEBUG_HEADER = xscale_debug.inc
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BUILT_SOURCES = $(DEBUG_HEADER)
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CLEANFILES = $(DEBUG_HEADER)
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$(DEBUG_HEADER): $(DEBUG_HANDLER) $(BIN2C)
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$(BIN2C) < $< > $@ || { rm -f $@; false; }
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METASOURCES = AUTO
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noinst_LTLIBRARIES = libtarget.la
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libtarget_la_SOURCES = \
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$(TARGET_CORE_SRC) \
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$(ARM_DEBUG_SRC) \
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$(ARMV4_5_SRC) \
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$(ARMV6_SRC) \
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$(ARMV7_SRC) \
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$(ARM_MISC_SRC) \
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$(AVR32_SRC) \
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$(MIPS32_SRC) \
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$(NDS32_SRC) \
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$(INTEL_IA32_SRC) \
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avrt.c \
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dsp563xx.c \
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dsp563xx_once.c \
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dsp5680xx.c \
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hla_target.c
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TARGET_CORE_SRC = \
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algorithm.c \
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register.c \
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image.c \
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breakpoints.c \
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target.c \
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target_request.c \
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testee.c \
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smp.c
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ARMV4_5_SRC = \
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armv4_5.c \
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armv4_5_mmu.c \
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armv4_5_cache.c \
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$(ARM7_9_SRC)
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ARM7_9_SRC = \
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arm7_9_common.c \
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arm7tdmi.c \
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arm720t.c \
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arm9tdmi.c \
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arm920t.c \
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arm966e.c \
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arm946e.c \
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arm926ejs.c \
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feroceon.c
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ARM_MISC_SRC = \
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fa526.c \
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xscale.c
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ARMV6_SRC = \
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arm11.c \
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arm11_dbgtap.c
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ARMV7_SRC = \
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armv7m.c \
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armv7m_trace.c \
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cortex_m.c \
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armv7a.c \
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cortex_a.c \
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ls1_sap.c
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ARM_DEBUG_SRC = \
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arm_dpm.c \
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arm_jtag.c \
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arm_disassembler.c \
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arm_simulator.c \
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arm_semihosting.c \
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arm_adi_v5.c \
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armv7a_cache.c \
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armv7a_cache_l2x.c \
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adi_v5_jtag.c \
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adi_v5_swd.c \
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embeddedice.c \
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trace.c \
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etb.c \
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etm.c \
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$(OOCD_TRACE_FILES) \
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etm_dummy.c
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AVR32_SRC = \
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avr32_ap7k.c \
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avr32_jtag.c \
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avr32_mem.c \
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avr32_regs.c
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MIPS32_SRC = \
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mips32.c \
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mips_m4k.c \
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mips32_pracc.c \
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mips32_dmaacc.c \
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mips_ejtag.c
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NDS32_SRC = \
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nds32.c \
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nds32_reg.c \
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nds32_cmd.c \
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nds32_disassembler.c \
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nds32_tlb.c \
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nds32_v2.c \
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nds32_v3_common.c \
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nds32_v3.c \
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nds32_v3m.c \
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nds32_aice.c
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INTEL_IA32_SRC = \
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quark_x10xx.c \
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quark_d20xx.c \
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lakemont.c \
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x86_32_common.c
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noinst_HEADERS = \
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algorithm.h \
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arm.h \
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arm_dpm.h \
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arm_jtag.h \
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arm_adi_v5.h \
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armv7a_cache.h \
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armv7a_cache_l2x.h \
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arm_disassembler.h \
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arm_opcodes.h \
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arm_simulator.h \
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arm_semihosting.h \
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arm7_9_common.h \
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arm7tdmi.h \
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arm720t.h \
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arm9tdmi.h \
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arm920t.h \
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arm926ejs.h \
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arm966e.h \
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arm946e.h \
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arm11.h \
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arm11_dbgtap.h \
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armv4_5.h \
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armv4_5_mmu.h \
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armv4_5_cache.h \
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armv7a.h \
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armv7m.h \
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armv7m_trace.h \
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avrt.h \
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dsp563xx.h \
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dsp563xx_once.h \
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dsp5680xx.h \
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breakpoints.h \
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cortex_m.h \
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cortex_a.h \
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embeddedice.h \
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etb.h \
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etm.h \
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etm_dummy.h \
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image.h \
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mips32.h \
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mips_m4k.h \
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mips_ejtag.h \
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mips32_pracc.h \
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mips32_dmaacc.h \
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oocd_trace.h \
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register.h \
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target.h \
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target_type.h \
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trace.h \
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target_request.h \
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trace.h \
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xscale.h \
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smp.h \
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avr32_ap7k.h \
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avr32_jtag.h \
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avr32_mem.h \
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avr32_regs.h \
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nds32.h \
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nds32_cmd.h \
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nds32_disassembler.h \
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nds32_edm.h \
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nds32_insn.h \
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nds32_reg.h \
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nds32_tlb.h \
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nds32_v2.h \
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nds32_v3_common.h \
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nds32_v3.h \
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nds32_v3m.h \
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nds32_aice.h \
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lakemont.h \
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x86_32_common.h
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ocddatadir = $(pkglibdir)
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nobase_dist_ocddata_DATA =
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MAINTAINERCLEANFILES = $(srcdir)/Makefile.in
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