forked from auracaster/openocd
bc72695f67
This represents months of continuing RISC-V work, with too many changes to list individually. Some improvements: * Fixed memory leaks. * Better handling of dbus timeouts. * Add `riscv expose_custom` command. * Somewhat deal with cache coherency. * Deal with more timeouts during block memory accesses. * Basic debug compliance test. * Tell gdb which watchpoint hit. * SMP support for use with -rtos hwthread * Add `riscv set_ir` Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4922 Tested-by: jenkins Reviewed-by: Philipp Guehring <pg@futureware.at> Reviewed-by: Liviu Ionescu <ilg@livius.net> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
76 lines
3.2 KiB
C
76 lines
3.2 KiB
C
#ifndef TARGET__RISCV__PROGRAM_H
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#define TARGET__RISCV__PROGRAM_H
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#include "riscv.h"
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#define RISCV_MAX_DEBUG_BUFFER_SIZE 32
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#define RISCV_REGISTER_COUNT 32
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#define RISCV_DSCRATCH_COUNT 2
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/* The various RISC-V debug specifications all revolve around setting up
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* program buffers and executing them on the target. This structure contains a
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* single program, which can then be executed on targets. */
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struct riscv_program {
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struct target *target;
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uint32_t debug_buffer[RISCV_MAX_DEBUG_BUFFER_SIZE];
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/* Number of 32-bit instructions in the program. */
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size_t instruction_count;
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/* Side effects of executing this program. These must be accounted for
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* in order to maintain correct executing of the target system. */
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bool writes_xreg[RISCV_REGISTER_COUNT];
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/* XLEN on the target. */
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int target_xlen;
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};
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/* Initializes a program with the header. */
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int riscv_program_init(struct riscv_program *p, struct target *t);
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/* Write the program to the program buffer. */
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int riscv_program_write(struct riscv_program *program);
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/* Executes a program, returning 0 if the program successfully executed. Note
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* that this may cause registers to be saved or restored, which could result to
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* calls to things like riscv_save_register which itself could require a
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* program to execute. That's OK, just make sure this eventually terminates.
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* */
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int riscv_program_exec(struct riscv_program *p, struct target *t);
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int riscv_program_load(struct riscv_program *p, struct target *t);
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/* Clears a program, removing all the state associated with it. */
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int riscv_program_clear(struct riscv_program *p, struct target *t);
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/* A lower level interface, you shouldn't use this unless you have a reason. */
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int riscv_program_insert(struct riscv_program *p, riscv_insn_t i);
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/* There is hardware support for saving at least one register. This register
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* doesn't need to be saved/restored the usual way, which is useful during
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* early initialization when we can't save/restore arbitrary registerrs to host
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* memory. */
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int riscv_program_save_to_dscratch(struct riscv_program *p, enum gdb_regno to_save);
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/* Helpers to assemble various instructions. Return 0 on success. These might
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* assemble into a multi-instruction sequence that overwrites some other
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* register, but those will be properly saved and restored. */
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int riscv_program_lwr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno a, int o);
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int riscv_program_lhr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno a, int o);
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int riscv_program_lbr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno a, int o);
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int riscv_program_swr(struct riscv_program *p, enum gdb_regno s, enum gdb_regno a, int o);
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int riscv_program_shr(struct riscv_program *p, enum gdb_regno s, enum gdb_regno a, int o);
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int riscv_program_sbr(struct riscv_program *p, enum gdb_regno s, enum gdb_regno a, int o);
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int riscv_program_csrr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno csr);
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int riscv_program_csrw(struct riscv_program *p, enum gdb_regno s, enum gdb_regno csr);
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int riscv_program_fence_i(struct riscv_program *p);
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int riscv_program_fence(struct riscv_program *p);
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int riscv_program_ebreak(struct riscv_program *p);
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int riscv_program_addi(struct riscv_program *p, enum gdb_regno d, enum gdb_regno s, int16_t i);
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#endif
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