Files
sw_openocd/src/target/espressif/esp_xtensa_semihosting.h
Erhan Kurubas bea4d65903 target/espressif: add semihosting support
ARM semihosting + some custom syscalls implemented for
Espressif chips (ESP32, ESP32-S2, ESP32-S3)

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ic8174cf1cd344fa16d619b7b8405c9650e869443
Reviewed-on: https://review.openocd.org/c/openocd/+/7074
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-03 21:27:17 +00:00

16 lines
581 B
C

/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* Copyright (c) 2020 Espressif Systems (Shanghai) Co. Ltd. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H
#define OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H
#include <target/target.h>
int esp_xtensa_semihosting_init(struct target *target);
int esp_xtensa_semihosting(struct target *target, int *retval);
#endif /* OPENOCD_TARGET_ESP_XTENSA_SEMIHOSTING_H */