forked from auracaster/openocd
d06ecba2e6
Microchip's PolarFire SoC has a RISC-V core complex with four application processors and one monitor processor. This basic configuration can be used to attach to all proccessor's or a single processor, specified by the run-time argument $COREID It can be used with most FTDI based debug interfaces and has been tested with interface/ftdi/olimex-arm-usb-tiny-h.cfg. Change-Id: I75dd965f1ce550807706d00fe17de887d36f0b02 Signed-off-by: Liam Fletcher <liam.fletcher@microchip.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8877 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
76 lines
2.0 KiB
INI
76 lines
2.0 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Target: MPFS PolarFire SoC-series processors by Microchip Technologies
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#
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# https://www.microchip.com/en-us/products/fpgas-and-plds/system-on-chip-fpgas/polarfire-soc-fpgas
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#
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME mpfs
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}
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# Process COREID variable
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if { ![exists COREID] } {
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set COREID -1
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}
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transport select jtag
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# PolarFire SoC (MPFS) hart id to name lookup table
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array set hart_names {
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0 e51
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1 u54_1
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2 u54_2
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3 u54_3
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4 u54_4
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}
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# MPFS devices table
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set mpfs_cpu_tap_info {
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MPFS025 0x0f8531cf
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MPFS095 0x0f8181cf
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MPFS160 0x0f8191cf
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MPFS250 0x0f81a1cf
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MPFS460 0x0f81b1cf
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RTPFS160 0x0f8991cf
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RTPFS460 0x0f89b1cf
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}
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proc expected_ids {tap_list} {
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set str ""
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dict for {key value} $tap_list {
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append str "-expected-id" " " $value " "
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}
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return $str
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}
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set irlen 8
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set expected_ids [expected_ids $mpfs_cpu_tap_info]
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eval jtag newtap $_CHIPNAME cpu -irlen $irlen $expected_ids -ignore-version
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if {$COREID == -1} {
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# Single debug connection to all HART's
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set _TARGETNAME_0 $_CHIPNAME.$hart_names(0)
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set _TARGETNAME_1 $_CHIPNAME.$hart_names(1)
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set _TARGETNAME_2 $_CHIPNAME.$hart_names(2)
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set _TARGETNAME_3 $_CHIPNAME.$hart_names(3)
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set _TARGETNAME_4 $_CHIPNAME.$hart_names(4)
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target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread
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target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 -rtos hwthread
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target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2 -rtos hwthread
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target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3 -rtos hwthread
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target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu -coreid 4 -rtos hwthread
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target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4
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} else {
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# Debug connection to a specific hart
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set _TARGETNAME_0 $_CHIPNAME.$hart_names($COREID)
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target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid $COREID
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}
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# Only TRSTn supported
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reset_config trst_only
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