forked from auracaster/openocd
382148e4dd
With the old checkpatch we cannot use the correct format for the SPDX tags in the file .c, in fact the C99 comments are not allowed and we had to use the block comment. With the new checkpatch, let's switch to the correct SPDX format. Change created automatically through the command: sed -i \ 's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \ $(find src/ contrib/ -name \*.c) Change-Id: I6da16506baa7af718947562505dd49606d124171 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7153 Tested-by: jenkins
151 lines
3.5 KiB
C
151 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* Copyright (C) 2009 by Marvell Semiconductors, Inc. *
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* Written by Nicolas Pitre <nico at marvell.com> *
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***************************************************************************/
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/*
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* NAND controller interface for Marvell Orion/Kirkwood SoCs.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "imp.h"
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#include "arm_io.h"
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#include <target/arm.h>
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struct orion_nand_controller {
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struct arm_nand_data io;
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uint32_t cmd;
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uint32_t addr;
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uint32_t data;
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};
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#define CHECK_HALTED \
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do { \
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if (target->state != TARGET_HALTED) { \
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LOG_ERROR("NAND flash access requires halted target"); \
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return ERROR_NAND_OPERATION_FAILED; \
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} \
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} while (0)
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static int orion_nand_command(struct nand_device *nand, uint8_t command)
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{
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struct orion_nand_controller *hw = nand->controller_priv;
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struct target *target = nand->target;
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CHECK_HALTED;
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target_write_u8(target, hw->cmd, command);
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return ERROR_OK;
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}
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static int orion_nand_address(struct nand_device *nand, uint8_t address)
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{
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struct orion_nand_controller *hw = nand->controller_priv;
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struct target *target = nand->target;
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CHECK_HALTED;
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target_write_u8(target, hw->addr, address);
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return ERROR_OK;
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}
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static int orion_nand_read(struct nand_device *nand, void *data)
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{
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struct orion_nand_controller *hw = nand->controller_priv;
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struct target *target = nand->target;
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CHECK_HALTED;
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target_read_u8(target, hw->data, data);
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return ERROR_OK;
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}
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static int orion_nand_write(struct nand_device *nand, uint16_t data)
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{
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struct orion_nand_controller *hw = nand->controller_priv;
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struct target *target = nand->target;
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CHECK_HALTED;
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target_write_u8(target, hw->data, data);
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return ERROR_OK;
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}
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static int orion_nand_slow_block_write(struct nand_device *nand, uint8_t *data, int size)
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{
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while (size--)
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orion_nand_write(nand, *data++);
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return ERROR_OK;
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}
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static int orion_nand_fast_block_write(struct nand_device *nand, uint8_t *data, int size)
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{
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struct orion_nand_controller *hw = nand->controller_priv;
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int retval;
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hw->io.chunk_size = nand->page_size;
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retval = arm_nandwrite(&hw->io, data, size);
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if (retval == ERROR_NAND_NO_BUFFER)
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retval = orion_nand_slow_block_write(nand, data, size);
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return retval;
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}
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static int orion_nand_reset(struct nand_device *nand)
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{
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return orion_nand_command(nand, NAND_CMD_RESET);
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}
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NAND_DEVICE_COMMAND_HANDLER(orion_nand_device_command)
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{
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struct orion_nand_controller *hw;
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uint32_t base;
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uint8_t ale, cle;
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if (CMD_ARGC != 3)
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return ERROR_COMMAND_SYNTAX_ERROR;
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hw = calloc(1, sizeof(*hw));
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if (!hw) {
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LOG_ERROR("no memory for nand controller");
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return ERROR_NAND_DEVICE_INVALID;
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}
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nand->controller_priv = hw;
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], base);
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cle = 0;
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ale = 1;
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hw->data = base;
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hw->cmd = base + (1 << cle);
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hw->addr = base + (1 << ale);
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hw->io.target = nand->target;
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hw->io.data = hw->data;
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hw->io.op = ARM_NAND_NONE;
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return ERROR_OK;
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}
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static int orion_nand_init(struct nand_device *nand)
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{
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return ERROR_OK;
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}
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struct nand_flash_controller orion_nand_controller = {
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.name = "orion",
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.usage = "<target_id> <NAND_address>",
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.command = orion_nand_command,
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.address = orion_nand_address,
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.read_data = orion_nand_read,
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.write_data = orion_nand_write,
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.write_block_data = orion_nand_fast_block_write,
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.reset = orion_nand_reset,
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.nand_device_command = orion_nand_device_command,
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.init = orion_nand_init,
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};
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