forked from auracaster/openocd
5723e54fa9
Now that nothing uses the old ETM handle any more, remove it. Add minimal header tweaks, letting non-ARM7 and non-ARM9 cores access ETM facilities. Now ARM11 could support standard ETM (and ETB) access as soon as it derives from "struct arm" ... its scanchain 6 is used access the ETM, just like ARM7 and ARM9. The Cortex parts (both M3 and A8) will need modified access methods (via ETM init parameters), so they use the DAP. Our first A8 target (OMAP3) needs that for both ETM and ETB, but the M3 ETM isn't very useful without SWO trace support (it's painfully stripped down), so that support won't be worth adding for a while. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
215 lines
7.2 KiB
C
215 lines
7.2 KiB
C
/***************************************************************************
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* Copyright (C) 2005, 2007 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2007 by Vincent Palatin *
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* vincent.palatin_openocd@m4x.org *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ETM_H
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#define ETM_H
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#include "trace.h"
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#include "arm_jtag.h"
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struct image_s;
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/* ETM registers (JTAG protocol) */
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enum
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{
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ETM_CTRL = 0x00,
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ETM_CONFIG = 0x01,
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ETM_TRIG_EVENT = 0x02,
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ETM_ASIC_CTRL = 0x03,
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ETM_STATUS = 0x04,
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ETM_SYS_CONFIG = 0x05,
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ETM_TRACE_RESOURCE_CTRL = 0x06,
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ETM_TRACE_EN_CTRL2 = 0x07,
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ETM_TRACE_EN_EVENT = 0x08,
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ETM_TRACE_EN_CTRL1 = 0x09,
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/* optional FIFOFULL */
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ETM_FIFOFULL_REGION = 0x0a,
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ETM_FIFOFULL_LEVEL = 0x0b,
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/* viewdata support */
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ETM_VIEWDATA_EVENT = 0x0c,
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ETM_VIEWDATA_CTRL1 = 0x0d,
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ETM_VIEWDATA_CTRL2 = 0x0e, /* optional */
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ETM_VIEWDATA_CTRL3 = 0x0f,
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/* N pairs of ADDR_{COMPARATOR,ACCESS} registers */
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ETM_ADDR_COMPARATOR_VALUE = 0x10,
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ETM_ADDR_ACCESS_TYPE = 0x20,
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/* N pairs of DATA_COMPARATOR_{VALUE,MASK} registers */
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ETM_DATA_COMPARATOR_VALUE = 0x30,
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ETM_DATA_COMPARATOR_MASK = 0x40,
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/* N quads of COUNTER_{RELOAD_{VALUE,EVENT},ENABLE,VALUE} registers */
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ETM_COUNTER_RELOAD_VALUE = 0x50,
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ETM_COUNTER_ENABLE = 0x54,
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ETM_COUNTER_RELOAD_EVENT = 0x58,
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ETM_COUNTER_VALUE = 0x5c,
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/* 6 sequencer event transitions */
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ETM_SEQUENCER_EVENT = 0x60,
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ETM_SEQUENCER_STATE = 0x67,
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/* N triggered outputs */
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ETM_EXTERNAL_OUTPUT = 0x68,
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/* N task contexts */
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ETM_CONTEXTID_COMPARATOR_VALUE = 0x6c,
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ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,
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};
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typedef struct etm_reg_s
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{
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uint32_t value;
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const struct etm_reg_info *reg_info;
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arm_jtag_t *jtag_info;
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} etm_reg_t;
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typedef enum
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{
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/* Port width */
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ETM_PORT_4BIT = 0x00,
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ETM_PORT_8BIT = 0x10,
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ETM_PORT_16BIT = 0x20,
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ETM_PORT_WIDTH_MASK = 0x70,
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/* Port modes */
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ETM_PORT_NORMAL = 0x00000,
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ETM_PORT_MUXED = 0x10000,
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ETM_PORT_DEMUXED = 0x20000,
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ETM_PORT_MODE_MASK = 0x30000,
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/* Clocking modes */
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ETM_PORT_FULL_CLOCK = 0x0000,
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ETM_PORT_HALF_CLOCK = 0x1000,
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ETM_PORT_CLOCK_MASK = 0x1000,
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} etm_portmode_t;
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typedef enum
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{
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/* Data trace */
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ETMV1_TRACE_NONE = 0x00,
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ETMV1_TRACE_DATA = 0x01,
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ETMV1_TRACE_ADDR = 0x02,
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ETMV1_TRACE_MASK = 0x03,
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/* ContextID */
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ETMV1_CONTEXTID_NONE = 0x00,
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ETMV1_CONTEXTID_8 = 0x10,
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ETMV1_CONTEXTID_16 = 0x20,
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ETMV1_CONTEXTID_32 = 0x30,
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ETMV1_CONTEXTID_MASK = 0x30,
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/* Misc */
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ETMV1_CYCLE_ACCURATE = 0x100,
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ETMV1_BRANCH_OUTPUT = 0x200
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} etmv1_tracemode_t;
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/* forward-declare ETM context */
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struct etm;
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typedef struct etm_capture_driver_s
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{
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char *name;
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int (*register_commands)(struct command_context_s *cmd_ctx);
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int (*init)(struct etm *etm_ctx);
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trace_status_t (*status)(struct etm *etm_ctx);
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int (*read_trace)(struct etm *etm_ctx);
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int (*start_capture)(struct etm *etm_ctx);
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int (*stop_capture)(struct etm *etm_ctx);
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} etm_capture_driver_t;
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enum
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{
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ETMV1_TRACESYNC_CYCLE = 0x1,
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ETMV1_TRIGGER_CYCLE = 0x2,
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};
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typedef struct etmv1_trace_data_s
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{
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uint8_t pipestat; /* bits 0-2 pipeline status */
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uint16_t packet; /* packet data (4, 8 or 16 bit) */
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int flags; /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */
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} etmv1_trace_data_t;
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/* describe a trace context
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* if support for ETMv2 or ETMv3 is to be implemented,
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* this will have to be split into version independent elements
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* and a version specific part
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*/
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typedef struct etm
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{
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target_t *target; /* target this ETM is connected to */
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reg_cache_t *reg_cache; /* ETM register cache */
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etm_capture_driver_t *capture_driver; /* driver used to access ETM data */
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void *capture_driver_priv; /* capture driver private data */
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uint32_t trigger_percent; /* how much trace buffer to fill after trigger */
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trace_status_t capture_status; /* current state of capture run */
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etmv1_trace_data_t *trace_data; /* trace data */
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uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
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etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
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etmv1_tracemode_t tracemode; /* type of info trace contains */
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int /*armv4_5_state_t*/ core_state; /* current core state */
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struct image_s *image; /* source for target opcodes */
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uint32_t pipe_index; /* current trace cycle */
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uint32_t data_index; /* cycle holding next data packet */
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bool data_half; /* port half on a 16 bit port */
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bool pc_ok; /* full PC has been acquired */
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bool ptr_ok; /* whether last_ptr is valid */
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uint8_t bcd_vers; /* e.g. 0x13 == ETMv1.3 */
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uint32_t config; /* cache of ETM_CONFIG value */
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uint32_t current_pc; /* current program counter */
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uint32_t last_branch; /* last branch address output */
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uint32_t last_branch_reason; /* type of last branch encountered */
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uint32_t last_ptr; /* address of the last data access */
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uint32_t last_instruction; /* index of last executed (to calc timings) */
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} etm_context_t;
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/* PIPESTAT values */
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typedef enum
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{
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STAT_IE = 0x0,
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STAT_ID = 0x1,
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STAT_IN = 0x2,
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STAT_WT = 0x3,
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STAT_BE = 0x4,
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STAT_BD = 0x5,
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STAT_TR = 0x6,
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STAT_TD = 0x7
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} etmv1_pipestat_t;
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/* branch reason values */
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typedef enum
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{
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BR_NORMAL = 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */
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BR_ENABLE = 0x1, /* Trace has been enabled */
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BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */
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BR_NODEBUG = 0x3, /* ARM has exited for debug state */
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BR_PERIOD = 0x4, /* Peridioc synchronization point (ETM >= v1.2)*/
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BR_RSVD5 = 0x5, /* reserved */
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BR_RSVD6 = 0x6, /* reserved */
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BR_RSVD7 = 0x7, /* reserved */
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} etmv1_branch_reason_t;
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reg_cache_t* etm_build_reg_cache(target_t *target,
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arm_jtag_t *jtag_info, etm_context_t *etm_ctx);
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int etm_setup(target_t *target);
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int etm_register_commands(struct command_context_s *cmd_ctx);
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#define ERROR_ETM_INVALID_DRIVER (-1300)
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#define ERROR_ETM_PORTMODE_NOT_SUPPORTED (-1301)
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#define ERROR_ETM_CAPTURE_INIT_FAILED (-1302)
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#define ERROR_ETM_ANALYSIS_FAILED (-1303)
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#endif /* ETM_H */
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