forked from auracaster/openocd
Antonio Borneo
da34e36cdb
The target nds32 and its companion adapter aice have not received
any real improvement since 2013.
It has been hard to keep them aligned during the evolution of
OpenOCD code, with no way for maintainers to really check if they
are still working.
No real documentation is present for them in OpenOCD.
The nds32 code triggers ~50 errors/warnings with scan-build.
The arch nds32 has been dropped from Linux kernel v5.18-rc1.
For all the reasons above, this code has been deprecated with
commit 2e5df83de7 ("nds32: deprecate it, together with aice
adapter driver") and tagged to be dropped before v0.13.0.
Let it r.i.p. in OpenOCD git history.
While there, drop from checkpatch list the camelcase symbols that
where only used in this code.
Change-Id: Ide52a217f2228e9da2f1cc5036c48f3536f26952
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7382
Tested-by: jenkins
232 lines
8.5 KiB
C
232 lines
8.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* Copyright (C) 2011 by Broadcom Corporation *
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* Evan Hunter - ehunter@broadcom.com *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "rtos.h"
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#include "target/armv7m.h"
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static const struct stack_register_offset rtos_standard_cortex_m3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
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{ ARMV7M_R0, 0x20, 32 }, /* r0 */
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{ ARMV7M_R1, 0x24, 32 }, /* r1 */
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{ ARMV7M_R2, 0x28, 32 }, /* r2 */
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{ ARMV7M_R3, 0x2c, 32 }, /* r3 */
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{ ARMV7M_R4, 0x00, 32 }, /* r4 */
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{ ARMV7M_R5, 0x04, 32 }, /* r5 */
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{ ARMV7M_R6, 0x08, 32 }, /* r6 */
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{ ARMV7M_R7, 0x0c, 32 }, /* r7 */
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{ ARMV7M_R8, 0x10, 32 }, /* r8 */
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{ ARMV7M_R9, 0x14, 32 }, /* r9 */
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{ ARMV7M_R10, 0x18, 32 }, /* r10 */
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{ ARMV7M_R11, 0x1c, 32 }, /* r11 */
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{ ARMV7M_R12, 0x30, 32 }, /* r12 */
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{ ARMV7M_R13, -2, 32 }, /* sp */
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{ ARMV7M_R14, 0x34, 32 }, /* lr */
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{ ARMV7M_PC, 0x38, 32 }, /* pc */
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{ ARMV7M_XPSR, 0x3c, 32 }, /* xPSR */
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};
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static const struct stack_register_offset rtos_standard_cortex_m4f_stack_offsets[] = {
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{ ARMV7M_R0, 0x24, 32 }, /* r0 */
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{ ARMV7M_R1, 0x28, 32 }, /* r1 */
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{ ARMV7M_R2, 0x2c, 32 }, /* r2 */
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{ ARMV7M_R3, 0x30, 32 }, /* r3 */
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{ ARMV7M_R4, 0x00, 32 }, /* r4 */
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{ ARMV7M_R5, 0x04, 32 }, /* r5 */
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{ ARMV7M_R6, 0x08, 32 }, /* r6 */
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{ ARMV7M_R7, 0x0c, 32 }, /* r7 */
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{ ARMV7M_R8, 0x10, 32 }, /* r8 */
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{ ARMV7M_R9, 0x14, 32 }, /* r9 */
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{ ARMV7M_R10, 0x18, 32 }, /* r10 */
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{ ARMV7M_R11, 0x1c, 32 }, /* r11 */
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{ ARMV7M_R12, 0x34, 32 }, /* r12 */
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{ ARMV7M_R13, -2, 32 }, /* sp */
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{ ARMV7M_R14, 0x38, 32 }, /* lr */
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{ ARMV7M_PC, 0x3c, 32 }, /* pc */
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{ ARMV7M_XPSR, 0x40, 32 }, /* xPSR */
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};
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static const struct stack_register_offset rtos_standard_cortex_m4f_fpu_stack_offsets[] = {
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{ ARMV7M_R0, 0x64, 32 }, /* r0 */
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{ ARMV7M_R1, 0x68, 32 }, /* r1 */
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{ ARMV7M_R2, 0x6c, 32 }, /* r2 */
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{ ARMV7M_R3, 0x70, 32 }, /* r3 */
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{ ARMV7M_R4, 0x00, 32 }, /* r4 */
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{ ARMV7M_R5, 0x04, 32 }, /* r5 */
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{ ARMV7M_R6, 0x08, 32 }, /* r6 */
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{ ARMV7M_R7, 0x0c, 32 }, /* r7 */
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{ ARMV7M_R8, 0x10, 32 }, /* r8 */
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{ ARMV7M_R9, 0x14, 32 }, /* r9 */
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{ ARMV7M_R10, 0x18, 32 }, /* r10 */
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{ ARMV7M_R11, 0x1c, 32 }, /* r11 */
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{ ARMV7M_R12, 0x74, 32 }, /* r12 */
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{ ARMV7M_R13, -2, 32 }, /* sp */
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{ ARMV7M_R14, 0x78, 32 }, /* lr */
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{ ARMV7M_PC, 0x7c, 32 }, /* pc */
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{ ARMV7M_XPSR, 0x80, 32 }, /* xPSR */
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};
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static const struct stack_register_offset rtos_standard_cortex_r4_stack_offsets[] = {
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{ 0, 0x08, 32 }, /* r0 (a1) */
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{ 1, 0x0c, 32 }, /* r1 (a2) */
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{ 2, 0x10, 32 }, /* r2 (a3) */
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{ 3, 0x14, 32 }, /* r3 (a4) */
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{ 4, 0x18, 32 }, /* r4 (v1) */
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{ 5, 0x1c, 32 }, /* r5 (v2) */
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{ 6, 0x20, 32 }, /* r6 (v3) */
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{ 7, 0x24, 32 }, /* r7 (v4) */
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{ 8, 0x28, 32 }, /* r8 (a1) */
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{ 10, 0x2c, 32 }, /* r9 (sb) */
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{ 11, 0x30, 32 }, /* r10 (sl) */
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{ 12, 0x34, 32 }, /* r11 (fp) */
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{ 13, 0x38, 32 }, /* r12 (ip) */
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{ 14, -2, 32 }, /* sp */
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{ 15, 0x3c, 32 }, /* lr */
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{ 16, 0x40, 32 }, /* pc */
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{ 17, -1, 96 }, /* FPA1 */
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{ 18, -1, 96 }, /* FPA2 */
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{ 19, -1, 96 }, /* FPA3 */
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{ 20, -1, 96 }, /* FPA4 */
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{ 21, -1, 96 }, /* FPA5 */
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{ 22, -1, 96 }, /* FPA6 */
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{ 23, -1, 96 }, /* FPA7 */
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{ 24, -1, 96 }, /* FPA8 */
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{ 25, -1, 32 }, /* FPS */
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{ 26, 0x04, 32 }, /* CSPR */
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};
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static target_addr_t rtos_generic_stack_align(struct target *target,
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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target_addr_t stack_ptr, int align)
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{
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target_addr_t new_stack_ptr;
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target_addr_t aligned_stack_ptr;
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new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
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stacking->stack_registers_size;
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aligned_stack_ptr = new_stack_ptr & ~((target_addr_t)align - 1);
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if (aligned_stack_ptr != new_stack_ptr &&
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stacking->stack_growth_direction == -1) {
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/* If we have a downward growing stack, the simple alignment code
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* above results in a wrong result (since it rounds down to nearest
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* alignment). We want to round up so add an extra align.
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*/
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aligned_stack_ptr += (target_addr_t)align;
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}
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return aligned_stack_ptr;
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}
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target_addr_t rtos_generic_stack_align8(struct target *target,
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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target_addr_t stack_ptr)
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{
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return rtos_generic_stack_align(target, stack_data,
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stacking, stack_ptr, 8);
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}
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/* The Cortex-M3 will indicate that an alignment adjustment
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* has been done on the stack by setting bit 9 of the stacked xPSR
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* register. In this case, we can just add an extra 4 bytes to get
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* to the program stack. Note that some places in the ARM documentation
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* make this a little unclear but the padding takes place before the
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* normal exception stacking - so xPSR is always available at a fixed
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* location.
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*
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* Relevant documentation:
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* Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
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* Cortex-M3 Devices Generic User Guide -> The Cortex-M3 Processor ->
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* Exception Model -> Exception entry and return -> Exception entry
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* Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
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* Cortex-M3 Devices Generic User Guide -> Cortex-M3 Peripherals ->
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* System control block -> Configuration and Control Register (STKALIGN)
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*
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* This is just a helper function for use in the calculate_process_stack
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* function for a given architecture/rtos.
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*/
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target_addr_t rtos_cortex_m_stack_align(struct target *target,
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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target_addr_t stack_ptr, size_t xpsr_offset)
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{
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const uint32_t ALIGN_NEEDED = (1 << 9);
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uint32_t xpsr;
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target_addr_t new_stack_ptr;
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new_stack_ptr = stack_ptr - stacking->stack_growth_direction *
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stacking->stack_registers_size;
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xpsr = (target->endianness == TARGET_LITTLE_ENDIAN) ?
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le_to_h_u32(&stack_data[xpsr_offset]) :
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be_to_h_u32(&stack_data[xpsr_offset]);
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if ((xpsr & ALIGN_NEEDED) != 0) {
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LOG_DEBUG("XPSR(0x%08" PRIx32 ") indicated stack alignment was necessary\r\n",
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xpsr);
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new_stack_ptr -= (stacking->stack_growth_direction * 4);
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}
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return new_stack_ptr;
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}
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static target_addr_t rtos_standard_cortex_m3_stack_align(struct target *target,
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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target_addr_t stack_ptr)
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{
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const int XPSR_OFFSET = 0x3c;
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return rtos_cortex_m_stack_align(target, stack_data, stacking,
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stack_ptr, XPSR_OFFSET);
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}
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static target_addr_t rtos_standard_cortex_m4f_stack_align(struct target *target,
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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target_addr_t stack_ptr)
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{
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const int XPSR_OFFSET = 0x40;
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return rtos_cortex_m_stack_align(target, stack_data, stacking,
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stack_ptr, XPSR_OFFSET);
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}
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static target_addr_t rtos_standard_cortex_m4f_fpu_stack_align(struct target *target,
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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target_addr_t stack_ptr)
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{
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const int XPSR_OFFSET = 0x80;
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return rtos_cortex_m_stack_align(target, stack_data, stacking,
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stack_ptr, XPSR_OFFSET);
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}
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const struct rtos_register_stacking rtos_standard_cortex_m3_stacking = {
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.stack_registers_size = 0x40,
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.stack_growth_direction = -1,
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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.calculate_process_stack = rtos_standard_cortex_m3_stack_align,
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.register_offsets = rtos_standard_cortex_m3_stack_offsets
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};
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const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking = {
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.stack_registers_size = 0x44,
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.stack_growth_direction = -1,
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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.calculate_process_stack = rtos_standard_cortex_m4f_stack_align,
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.register_offsets = rtos_standard_cortex_m4f_stack_offsets
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};
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const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking = {
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.stack_registers_size = 0xcc,
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.stack_growth_direction = -1,
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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.calculate_process_stack = rtos_standard_cortex_m4f_fpu_stack_align,
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.register_offsets = rtos_standard_cortex_m4f_fpu_stack_offsets
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};
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const struct rtos_register_stacking rtos_standard_cortex_r4_stacking = {
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.stack_registers_size = 0x48,
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.stack_growth_direction = -1,
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.num_output_registers = 26,
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.calculate_process_stack = rtos_generic_stack_align8,
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.register_offsets = rtos_standard_cortex_r4_stack_offsets
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};
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