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sw_openocd
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7c989698a14b2626702ffb8812e78c7fd274af75
sw_openocd
/
src
/
target
/
riscv
T
History
Tim Newsome
7c989698a1
WIP better CSR names, and include only existing
...
Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
2017-12-19 10:41:48 -08:00
..
asm.h
target/riscv/asm.h: use tab for indentation
2017-10-03 00:36:22 +03:00
batch.c
MemTest64 passes.
2017-10-17 11:15:51 -07:00
batch.h
clang fix, don't allow unaligned uint64_t pointers
2017-09-18 14:56:46 -07:00
debug_defines.h
Pay attention to impebreak.
2017-10-18 14:21:23 -07:00
encoding.h
Update encoding.h.
2017-11-27 13:23:33 -08:00
gdb_regs.h
Share register numbers between 0.11 and 0.13.
2017-09-30 13:13:03 -07:00
opcodes.h
Update encoding.h.
2017-11-27 13:23:33 -08:00
program.c
Remove unused functionality.
2017-10-23 14:45:58 -07:00
program.h
Remove unused functionality.
2017-10-23 14:45:58 -07:00
riscv-011.c
Fix compile warnings.
2017-10-04 16:02:30 -07:00
riscv-013.c
WIP better CSR names, and include only existing
2017-12-19 10:41:48 -08:00
riscv.c
WIP. Hide FPRs if the hart doesn't support F/D.
2017-12-19 10:41:48 -08:00
riscv.h
make all
debug tests now pass.
2017-12-19 10:41:48 -08:00