forked from auracaster/openocd
8e11797618
- add xpi flash support for hpmicro devices Change-Id: I3531fdf20a34561c6f3fe6ac0b9af988d483aae7 Signed-off-by: Ryan QIAN <jianghao.qian@hpmicro.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8695 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
255 lines
9.3 KiB
C
255 lines
9.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2021 HPMicro
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*/
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#ifndef HPM_ROMAPI_XPI_DEF_H
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#define HPM_ROMAPI_XPI_DEF_H
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/**
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* @brief XPI ROM APIs
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* @defgroup xpi_interface XPI driver APIs
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* @{
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*/
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#include "hpm_common.h"
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/**
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* @brief XPI Read Sample Clock source options
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*/
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enum xpi_rxclksrc_type_t {
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xpi_rxclksrc_internal_loopback = 0, /**< Internal loopback */
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xpi_rxclksrc_dqs_loopback = 1, /**< Loopback from DQS pad */
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xpi_rxclksrc_external_dqs = 3, /**< Read is driven by External DQS pad */
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};
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/**
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* @brief XPI pad definitions
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*/
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#define XPI_1PAD (0U) /**< Single pad */
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#define XPI_2PADS (1U) /**< Dual pads */
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#define XPI_4PADS (2U) /**< Quad pads */
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#define XPI_8PADS (3U) /**< Octal pads */
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/**
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* @brief XPI IO pin group options
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*/
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enum xpi_io_group_t {
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xpi_io_1st_group, /**< First/Primary group */
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xpi_io_2nd_group, /**< Second/Secondary group */
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};
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/**
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* @brief XPI Transfer Channel type definitions
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*/
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enum xpi_xfer_channel_t {
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xpi_xfer_channel_a1, /**< The address is based on the device connected to Channel A1 */
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xpi_xfer_channel_a2, /**< The address is based on the device connected to Channel A2 */
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xpi_xfer_channel_b1, /**< The address is based on the device connected to Channel B1 */
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xpi_xfer_channel_b2, /**< The address is based on the device connected to Channel B2 */
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xpi_xfer_channel_auto, /**< The channel is auto determined */
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};
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/**
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* @brief XPI Channel definitions
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*/
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enum xpi_channel_t {
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xpi_channel_a1, /**< Port: Channel A1 */
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xpi_channel_a2, /**< Port: Channel A2 */
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xpi_channel_b1, /**< Port: Channel B1 */
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xpi_channel_b2, /**< Port: Channel B2 */
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};
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/**
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* @brief XPI APB Transfer type
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*/
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enum xpi_apb_xfer_type_t {
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xpi_apb_xfer_type_cmd, /**< APB Command Type: Command only */
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xpi_apb_xfer_type_config, /**< APB Command Type: Configuration */
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xpi_apb_xfer_type_read, /**< APB Command Type: Read */
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xpi_apb_xfer_type_write, /**< APB Command Type: Write */
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};
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/**
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* @brief XPI Xfer Mode
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*/
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enum xpi_xfer_mode_t {
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xpi_xfer_mode_polling, /**< Transfer mode: Polling */
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xpi_xfer_mode_dma, /**< Transfer mode: DMA */
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xpi_xfer_mode_interrupt, /**< Transfer mode: Interrupt */
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};
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/**
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* @brief XPI Xfer context
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*/
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struct xpi_xfer_ctx_t {
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uint32_t addr; /**< device address for XPI transfer */
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uint8_t channel; /**< channel for XPI transfer */
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uint8_t cmd_type; /**< command type for XPI transfer */
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uint8_t seq_idx; /**< Sequence index for XPI transfer */
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uint8_t seq_num; /**< Sequence number for XPI transfer */
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uint32_t *buf; /**< Buffer for XPI transfer */
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uint32_t xfer_size; /**< Transfer size in bytes */
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};
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/**
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* @brief XPI instruction sequence
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*/
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struct xpi_instr_seq_t {
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uint32_t entry[4];
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};
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/**
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* @brief XPI Phase definitions
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*/
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#define XPI_PHASE_STOP (0x00U) /**< Phase: Stop */
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#define XPI_PHASE_CMD_SDR (0x01U) /**< Phase: Send CMD in SDR mode */
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#define XPI_PHASE_RADDR_SDR (0x02U) /**< Phase: Send Row Address in SDR Mode */
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#define XPI_PHASE_CADDR_SDR (0x03U) /**< Phase: Send Column Address in SDR Mode */
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#define XPI_PHASE_MODE4_SDR (0x06U) /**< Phase: Send Mode 4 in SDR Mode */
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#define XPI_PHASE_MODE8_SDR (0x07U) /**< Phase: Send Mode 8 in SDR Mode */
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#define XPI_PHASE_WRITE_SDR (0x08U) /**< Phase: Write data in SDR Mode */
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#define XPI_PHASE_READ_SDR (0x09U) /**< Phase: Read data in SDR Mode */
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#define XPI_PHASE_DUMMY_SDR (0X0CU) /**< Phase: Send Dummy in SDR Mode */
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#define XPI_PHASE_DUMMY_RWDS_SDR (0x0DU) /**< Phase: Send Dummy RWDS in SDR Mode */
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#define XPI_PHASE_CMD_DDR (0x21U) /**< Phase: Send CMD in DDR Mode */
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#define XPI_PHASE_RADDR_DDR (0x22U) /**< Phase: Send Raw Address in DDR Mode */
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#define XPI_PHASE_CADDR_DDR (0x23U) /**< Phase: Send Column address in DDR Mode */
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#define XPI_PHASE_MODE4_DDR (0x26U) /**< Phase: Send Mode 4 in DDR Mode */
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#define XPI_PHASE_MODE8_DDR (0x27U) /**< Phase: Send Mode 8 in DDR Mode */
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#define XPI_PHASE_WRITE_DDR (0x28U) /**< Phase: Write data in DDR Mode */
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#define XPI_PHASE_READ_DDR (0x29U) /**< Phase: Read data in SDR Mode */
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#define XPI_PHASE_DUMMY_DDR (0x2CU) /**< Phase: Send DUMMY in DDR Mode */
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#define XPI_PHASE_DUMMY_RWDS_DDR (0x2DU) /**< Phase: Send DUMMY RWDS in DDR Mode */
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/**
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* @brief XPI API command error codes
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*/
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enum {
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status_xpi_apb_jump_on_cs = MAKE_STATUS(status_group_xpi, 1),
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status_xpi_apb_unknown_inst = MAKE_STATUS(status_group_xpi, 2),
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status_xpi_apb_dummy_sdr_in_ddr_seq = MAKE_STATUS(status_group_xpi, 3),
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status_xpi_apb_dummy_ddr_in_sdr_seq = MAKE_STATUS(status_group_xpi, 4),
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status_xpi_apb_exceed_addr_range = MAKE_STATUS(status_group_xpi, 5),
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status_xpi_apb_seq_timeout = MAKE_STATUS(status_group_xpi, 6),
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status_xpi_apb_cross_boundary = MAKE_STATUS(status_group_xpi, 7),
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};
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/**
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* @brief Delay line definitions
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*/
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enum {
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xpi_dll_half_cycle = 0xFU,
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xpi_dll_quarter_cycle = 0x7U,
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xpi_dll_sdr_default_cycle = xpi_dll_half_cycle,
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xpi_dll_ddr_default_cycle = xpi_dll_quarter_cycle,
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};
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/**
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* @brief XPI configuration structure
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*/
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struct xpi_config_t {
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uint8_t rxclk_src; /**< Read sample clock source */
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uint8_t reserved0[7]; /**< Reserved */
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uint8_t tx_watermark_in_dwords; /**< Tx watermark in double words */
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uint8_t rx_watermark_in_dwords; /**< Rx watermark in double words */
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uint8_t enable_differential_clk; /**< Enable differential clock */
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uint8_t reserved1[5]; /**< Reserved */
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uint32_t access_flags; /**< Access flags */
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};
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/**
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* @brief XPI Device Configuration structure
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*/
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struct xpi_device_config_t {
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uint32_t size_in_kbytes; /**< Device size in kbytes */
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uint32_t serial_root_clk_freq; /**< XPI serial root clock frequency */
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uint8_t enable_write_mask; /**< Enable write mask, typically for PSRAM/HyperRAM */
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uint8_t data_valid_time; /**< Data valid time, Unit 0.1ns */
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uint8_t reserved0[2];
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uint8_t cs_hold_time; /**< CS hold time, cycles in terms of FLASH clock */
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uint8_t cs_setup_time; /**< CS setup time, cycles in terms of FLASH clock */
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uint16_t cs_interval; /**< CS interval, cycles in terms of FLASH clock */
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uint8_t reserved1;
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uint8_t column_addr_size; /**< Column address bits */
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uint8_t enable_word_address; /**< Enable word address, for HyperFLASH/HyperRAM */
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uint8_t dly_target; /**< Delay target */
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uint8_t ahb_write_seq_idx; /**< AHB write sequence index */
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uint8_t ahb_write_seq_num; /**< AHB write sequence number */
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uint8_t ahb_read_seq_idx; /**< AHB read sequence index */
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uint8_t ahb_read_seq_num; /**< AHB read sequence number */
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uint8_t ahb_write_wait_interval; /**< AHB write wait interval, in terms of FLASH clock */
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uint8_t reserved2[3];
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};
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/**
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* @brief SUB Instruction
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* @param [in] phase Name
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* @param [in] pad Pad for Phase
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* @param [in] op Operand for Phase
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*/
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#define SUB_INSTR(phase, pad, op) ((uint32_t)(((uint16_t)(phase) << 10) | ((uint16_t)(pad) << 8) | ((uint16_t)(op))))
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/**
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* @brief Generate a single word INSTRUCTION sequence word
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* @note Here intentionally use the MACRO because when the arguments are constant value, the compiler
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* can generate the const entry word during pre-processing
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*/
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#define XPI_INSTR_SEQ(phase0, pad0, op0, phase1, pad1, op1) \
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(SUB_INSTR(phase0, pad0, op0) | (SUB_INSTR(phase1, pad1, op1) << 16))
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struct xpi_ahb_buffer_cfg_t {
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struct {
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uint8_t priority; /* Offset: 0x00 */
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uint8_t master_idx; /* Offset: 0x01 */
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uint8_t buf_size_in_dword; /* Offset: 0x02 */
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bool enable_prefetch; /* Offset: 0x03 */
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} entry[8];
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};
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/**
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* @brief XPI driver interface
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*/
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struct xpi_driver_interface_t {
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/**< XPI driver interface: version */
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uint32_t version;
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/**< XPI driver interface: get default configuration */
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hpm_stat_t (*get_default_config)(struct xpi_config_t *xpi_config);
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/**< XPI driver interface: get default device configuration */
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hpm_stat_t (*get_default_device_config)(struct xpi_device_config_t *dev_config);
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/**< XPI driver interface: initialize the XPI using xpi_config */
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hpm_stat_t (*init)(uint32_t *base, struct xpi_config_t *xpi_config);
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/**< XPI driver interface: configure the AHB buffer */
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hpm_stat_t (*config_ahb_buffer)(uint32_t *base, struct xpi_ahb_buffer_cfg_t *ahb_buf_cfg);
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/**< XPI driver interface: configure the device */
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hpm_stat_t (*config_device)(uint32_t *base, struct xpi_device_config_t *dev_cfg, enum xpi_channel_t channel);
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/**< XPI driver interface: update instruction talbe */
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hpm_stat_t (*update_instr_table)(uint32_t *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num);
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/**< XPI driver interface: transfer command/data using block interface */
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hpm_stat_t (*transfer_blocking)(uint32_t *base, struct xpi_xfer_ctx_t *xfer);
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/**< Software reset the XPI controller */
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void (*software_reset)(uint32_t *base);
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/**< XPI driver interface: Check whether IP is idle */
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bool (*is_idle)(uint32_t *base);
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/**< XPI driver interface: update delay line setting */
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void (*update_dllcr)(uint32_t *base,
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uint32_t serial_root_clk_freq,
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uint32_t data_valid_time,
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enum xpi_channel_t channel,
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uint32_t dly_target);
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/**< XPI driver interface: Get absolute address for APB transfer */
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hpm_stat_t
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(*get_abs_apb_xfer_addr)(uint32_t *base, enum xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr);
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};
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/**
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* @}
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*/
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#endif /* HPM_ROMAPI_XPI_DEF_H */
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