forked from auracaster/openocd
22a7bda336
Corrected the include path for max32xxx_common.cfg in some files. Cleaned up and standarised some comments in the max32... files. Change-Id: I94dcc7ba6868bdd9730f03d3aa76fcdbbae33c3e Signed-off-by: Mark O'Donovan <shiftee@posteo.net> Reviewed-on: https://review.openocd.org/c/openocd/+/9323 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
47 lines
1.2 KiB
INI
47 lines
1.2 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Maxim Integrated MAX32690 - Arm Cortex-M4F @ 120MHz
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# Set the reset pin configuration
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reset_config srst_only
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adapter srst pulse_width 2
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# Set flash parameters
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set FLASH_BASE 0x10000000
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set FLASH_SIZE 0x300000
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set FLC_BASE 0x40029000
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set FLASH_SECTOR 0x4000
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set FLASH_CLK 60
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set FLASH_OPTIONS 0x01
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# Use Serial Wire Debug
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transport select swd
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source [find target/max32xxx_common.cfg]
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# Add additional flash bank
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set FLASH_BASE 0x10300000
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set FLASH_SIZE 0x40000
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set FLC_BASE 0x40029400
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set FLASH_SECTOR 0x2000
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flash bank $_CHIPNAME.flash1 max32xxx $FLASH_BASE $FLASH_SIZE 0 0 $_CHIPNAME.cpu \
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$FLC_BASE $FLASH_SECTOR $FLASH_CLK $FLASH_OPTIONS
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# Early revisions of the MAX32690 will disable SWD upon reset. There are reserved address locations
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# in the ROM code that can be used to insert breakpoints.
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# This workaround will enable SWD for affected revisions.
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$_CHIPNAME.cpu configure -event reset-assert-pre {
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if {$halt} {
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catch {bp 0x0000FFF4 2 hw}
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}
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}
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$_CHIPNAME.cpu configure -event reset-deassert-post {
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if {$halt} {
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$::_CHIPNAME.cpu arp_poll
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$::_CHIPNAME.cpu arp_poll
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$::_CHIPNAME.cpu arp_halt
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rbp 0x0000FFF4
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}
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}
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