forked from auracaster/openocd
9c91ce8d24
This is ANGIE's firmware and bitstream code. The 'Embeded C' code is based on the openULINK project. The hdl bitstream source code is for the spartan-6 FPGA included in ANGIE. Since ANGIE has a different microcontroller (EZ-USB FX2) than openULINK (EZ-USB AN2131), the registers file (reg_ezusb.h) has been changed completely, so are the descriptors, interruptions and the endpoints configuration. Change-Id: I70590c7c58bac6f1939c5ffba57e87d86850664d Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7701 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
36 lines
1.2 KiB
Plaintext
36 lines
1.2 KiB
Plaintext
## SPDX-License-Identifier: BSD-3-Clause
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##--------------------------------------------------------------------------
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## Project Context: nanoXplore USB-JTAG Adapter Board, Spartan6
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## Design Name: NJTAG USB-JTAG Adapter FPGA source code
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## Module Name: _angie_openocd.ucf
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## Target Device: XC6SLX9-2 TQ144
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## Tool versions: ISE Webpack 13.2 -> 14.2
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## Author: Ahmed BOUDJELIDA nanoXplore SAS
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##--------------------------------------------------------------------------
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# WARNING: PullUps on JTAG inputs should be enabled after configuration
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# (bitgen option) since the pins are not connected.
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net TRST LOC = 'P48' ;
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net TMS LOC = 'P43' ;
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net TCK LOC = 'P44' ;
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net TDI LOC = 'P45' ;
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net TDO LOC = 'P46' ;
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net SRST LOC = 'P61' ;
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net SI_TDO LOC = 'P16' ;
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net SO_TRST LOC = 'P32' ;
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net SO_TMS LOC = 'P27' ;
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net SO_TCK LOC = 'P30' ;
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net SO_TDI LOC = 'P26' ;
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net SO_SRST LOC = 'P12' ;
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net ST_0 LOC = 'P29' ;
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net ST_1 LOC = 'P21' ;
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net ST_2 LOC = 'P11' ;
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net FTP<0> LOC = 'P121' ;
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net FTP<1> LOC = 'P120' ;
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net FTP<2> LOC = 'P119' ;
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net FTP<3> LOC = 'P116' ;
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net FTP<4> LOC = 'P111' ;
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net FTP<5> LOC = 'P112' ;
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net FTP<6> LOC = 'P115' ;
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net FTP<7> LOC = 'P114' ;
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