Sean Anderson b61eae1962 cpld: altera-epm240: Increase adapter speed ...

According to the datasheet, the minimum clock period with Vccio1 = 1.5V
(the lowest voltage supported) is 143ns, or around 6MHz. Set the default
adapter speed to 5 MHz.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de
Reviewed-on: https://review.openocd.org/c/openocd/+/6847
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

2022-02-26 15:29:52 +00:00

..

altera-5m570z-cpld.cfg

tcl/cpld: add config file for Altera 5M570Z CPLD (MAXV family)

2017-05-09 21:41:46 +01:00

altera-epm240.cfg

cpld: altera-epm240: Increase adapter speed

2022-02-26 15:29:52 +00:00

jtagspi.cfg

jtagspi: new protocol that includes transfer length

2018-01-13 19:36:42 +00:00

lattice-lc4032ze.cfg

Add config file for Lattice LC4032ZE CPLD (ispMACH 4000ZE family)

2012-07-17 08:29:32 +00:00

xilinx-xc6s.cfg

tcl: Support for reading "Device DNA" from Spartan 6 devices.

2015-10-21 09:11:48 +01:00

xilinx-xc7.cfg

xilinx-xc7: Add additional IDCODEs.

2018-10-27 14:37:43 +01:00

xilinx-xcf-p.cfg

XCF (Xilinx platfrom flash) support.

2018-01-13 09:13:14 +00:00

xilinx-xcf-s.cfg

XCF (Xilinx platfrom flash) support.

2018-01-13 09:13:14 +00:00

xilinx-xcr3256.cfg

Xilinx xcr3256.cfg basic config script

2009-10-12 15:12:35 +02:00

xilinx-xcu.cfg

xilinx-xcu: add Xilinx Ultrascale tap data

2018-03-30 10:07:49 +01:00