forked from auracaster/openocd
c7073853eb
We want to keep the tri-state buffers located between the FPGA and the board, in 'Z' state until we launch an i2c connection. We launch an i2c start condition, make the SCL direction 'OUT' to start the i2c protocol and at the end of the i2c connection at the stop condition, we re-make the tri-state buffers at 'Z' state. Change-Id: Ic597a70d0427832547f6b539864c24ce20a18c64 Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7989 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
51 lines
1.4 KiB
Plaintext
51 lines
1.4 KiB
Plaintext
## SPDX-License-Identifier: BSD-3-Clause
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##--------------------------------------------------------------------------
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## Project Context: nanoXplore USB-JTAG Adapter Board, Spartan6
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## Design Name: NJTAG USB-JTAG Adapter FPGA source code
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## Module Name: _angie_openocd.ucf
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## Target Device: XC6SLX9-2 TQ144
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## Tool versions: ISE Webpack 13.2 -> 14.2
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## Author: Ahmed BOUDJELIDA nanoXplore SAS
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##--------------------------------------------------------------------------
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# WARNING: PullUps on JTAG inputs should be enabled after configuration
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# (bitgen option) since the pins are not connected.
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net TRST LOC = 'P48' ;
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net TMS LOC = 'P43' ;
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net TCK LOC = 'P44' ;
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net TDI LOC = 'P45' ;
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net TDO LOC = 'P46' ;
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net SRST LOC = 'P61' ;
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net SDA LOC = 'P50' ;
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net SCL LOC = 'P51' ;
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net SDA_DIR LOC = 'P56' ;
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net SCL_DIR LOC = 'P57' ;
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net SI_TDO LOC = 'P16' ;
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net SO_TRST LOC = 'P32' ;
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net SO_TMS LOC = 'P27' ;
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net SO_TCK LOC = 'P30' ;
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net SO_TDI LOC = 'P26' ;
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net SO_SRST LOC = 'P12' ;
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net SO_SDA_OUT LOC = 'P140' ;
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net SO_SDA_IN LOC = 'P1' ;
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net SO_SCL LOC = 'P137';
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net ST_0 LOC = 'P29' ;
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net ST_1 LOC = 'P21' ;
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net ST_2 LOC = 'P11' ;
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net ST_4 LOC = 'P134' ;
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net ST_5 LOC = 'P139' ;
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net FTP<0> LOC = 'P121' ;
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net FTP<1> LOC = 'P120' ;
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net FTP<2> LOC = 'P119' ;
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net FTP<3> LOC = 'P116' ;
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net FTP<4> LOC = 'P111' ;
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net FTP<5> LOC = 'P112' ;
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net FTP<6> LOC = 'P115' ;
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net FTP<7> LOC = 'P114' ;
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