Files
sw_openocd/src/target/riscv
Tim Newsome b04d5e8821 Read idle, and test all debug RAM.
Read dtmcontrol's idle field to decide how many run-test/idle cycles are
required to communicate with the target.

In riscv_examine(), write and read all of Debug RAM to check the target
is at least somewhat sane.

Change-Id: Ieedb7a50418fa1f5e0d456cde53c52f7fc51662b
2016-09-27 13:06:32 -07:00
..
2016-09-23 14:16:24 -07:00
2016-09-27 13:06:32 -07:00