Jesse Sheridan 0ef5144c32 target/riscv: Implement get_gdb_arch() ...

Change-Id: I5f4ab5243104df41031950682f688f2448a09b17
Signed-off-by: Jesse Sheridan <jesse.sheridan@gmail.com>
Reviewed-on: http://openocd.zylin.com/6322
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

2021-06-26 14:38:59 +01:00

..

asm.h

Upstream tons of RISC-V changes.

2020-10-14 05:43:05 +01:00

batch.c

Upstream tons of RISC-V changes.

2020-10-14 05:43:05 +01:00

batch.h

Upstream tons of RISC-V changes.

2020-10-14 05:43:05 +01:00

debug_defines.h

Upstream tons of RISC-V changes.

2020-10-14 05:43:05 +01:00

encoding.h

Upstream tons of RISC-V changes.

2020-10-14 05:43:05 +01:00

gdb_regs.h

Upstream tons of RISC-V changes.

2020-10-14 05:43:05 +01:00

Makefile.am

Add RISC-V support.

2018-07-24 13:07:26 +01:00

opcodes.h

Upstream tons of RISC-V changes.

2020-10-14 05:43:05 +01:00

program.c

Upstream tons of RISC-V changes.

2020-10-14 05:43:05 +01:00

program.h

Upstream tons of RISC-V changes.

2020-10-14 05:43:05 +01:00

riscv_semihosting.c

semihosting: print the semihosting operation id

2020-11-07 20:50:16 +00:00

riscv-011.c

riscv: replace macro DIM() with ARRAY_SIZE()

2021-05-22 10:11:41 +01:00

riscv-013.c

riscv: replace macro DIM() with ARRAY_SIZE()

2021-05-22 10:11:41 +01:00

riscv.c

target/riscv: Implement get_gdb_arch()

2021-06-26 14:38:59 +01:00

riscv.h

target/register: use an array of uint8_t for register's value

2020-12-05 23:18:37 +00:00