forked from auracaster/openocd
c0fc8f93f1
NAND support for DaVinci-family drivers, with HW ECC support. Declare the NAND chip on the DM355 EVM board. Currently tested on DM355 for Linux interop using the standard large page (2KB) chip in the EVM socket; "hwecc1" and "hwecc4" work fine. (Using hwecc4 relies on patches that haven't quite made it through the Linux-MTD bottlenecks yet.) Not yet tested: 1-bit on small-page (although it's hard to see how that could fail); 4-bit on small page (picky layout issues); the "hwecc_infix" mode (primarily for older boot ROMs; testing there is blocked on having new bootloader code). git-svn-id: svn://svn.berlios.de/openocd/trunk@1903 b42882b7-edfa-0310-969c-e2dbd0fdcd60
120 lines
3.2 KiB
INI
120 lines
3.2 KiB
INI
#
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# DM355 EVM board
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# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
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# http://c6000.spectrumdigital.com/evmdm355/
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source [find target/ti_dm355.cfg]
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reset_config trst_and_srst separate
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# NOTE: disable or replace this call to dm355evm_init if you're
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# debugging new UBL code from SRAM.
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$_TARGETNAME configure -event reset-init { dm355evm_init }
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#
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# This post-reset init is called when the MMU isn't active, all IRQs
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# are disabled, etc. It should do most of what a UBL does, except for
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# loading code (like U-Boot) into DRAM and running it.
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#
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proc dm355evm_init {} {
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global dm355
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puts "Initialize DM355 EVM board"
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# CLKIN = 24 MHz ... can't talk quickly to ARM yet
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jtag_khz 1500
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########################
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# PLL1 = 432 MHz (/8, x144)
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# ...SYSCLK1 = 216 MHz (/2) ... ARM, MJCP
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# ...SYSCLK2 = 108 MHz (/4) ... Peripherals
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# ...SYSCLK3 = 27 MHz (/16) ... VPBE, DAC
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# ...SYSCLK4 = 108 MHz (/4) ... VPSS
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# pll1.{prediv,div1,div2} are fixed
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# pll1.postdiv set in MISC (for *this* speed grade)
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set addr [dict get $dm355 pllc1]
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set pll_divs [dict create]
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dict set pll_divs div3 16
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dict set pll_divs div4 8
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pll_setup $addr 144 $pll_divs
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# ARM is now running at 216 MHz, so JTAG can go faster
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jtag_khz 20000
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########################
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# PLL2 = 342 MHz (/8, x114)
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# ....SYSCLK1 = 342 MHz (/1) ... DDR PHY at 171 MHz, 2x clock
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# pll2.{postdiv,div1} are fixed
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set addr [dict get $dm355 pllc2]
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set pll_divs [dict create]
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dict set pll_divs prediv 8
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pll_setup $addr 114 $pll_divs
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########################
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# PINMUX
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# All Video Inputs
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davinci_pinmux $dm355 0 0x00007f55
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# All Video Outputs
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davinci_pinmux $dm355 1 0x00145555
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# EMIFA (NOTE: more could be set up for use as GPIOs)
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davinci_pinmux $dm355 2 0x00000c08
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# SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
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davinci_pinmux $dm355 3 0x1bff55ff
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# MMC/SD0 instead of MS; SPI0
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davinci_pinmux $dm355 4 0x00000000
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########################
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# PSC setup (minimal)
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# DDR EMIF/13, AEMIF/14, UART0/19
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psc_enable 13
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psc_enable 14
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psc_enable 19
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psc_go
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########################
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# DDR2 EMIF
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# FIXME setup
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########################
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# ASYNC EMIF
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set addr [dict get $dm355 a_emif]
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# slow/pessimistic timings
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set nand_timings 0x40400204
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# fast (25% faster page reads)
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#set nand_timings 0x0400008c
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# AWCCR
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mww [expr $addr + 0x04] 0xff
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# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
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mww [expr $addr + 0x10] $nand_timings
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# CS1 == dm9000 Ethernet
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mww [expr $addr + 0x14] 0x00a00505
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# NANDFCR -- only CS0 has NAND
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mww [expr $addr + 0x60] 0x01
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########################
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# UART0
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# FIXME setup
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}
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# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
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#
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# NOTE: "hwecc4" here presumes that if you're using the standard 2GB NAND
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# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
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# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
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# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
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nand device davinci 0 0x02000000 hwecc4 0x01e10000
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nand device davinci 0 0x02004000 hwecc4 0x01e10000
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# FIXME
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# - support writing UBL with its header (new layout only with new ROMs)
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# - support writing ABL/U-Boot with its header (new layout)
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