forked from auracaster/openocd
c3ec1940b5
L0 is cortex m0+, so different id codes, SWD only, different addresses for the clock speedup. It has no endian options, no boundary scan. Removed all L0 specific portions from L1 files, and renamed files to clarify their purpose. The deprecated stm32lx_stlink.cfg is kept as is, as it is only around for backwards compatibility with prior releases. Tested on STM32L053 Discovery and STM32L151 Discovery. Has _not_ been tested with jtag on L1. Change-Id: I8eea890d2f92a302d9e9c8a8832d218ee1b6bcfc Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2405 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
9 lines
253 B
INI
9 lines
253 B
INI
source [find target/stm32l1.cfg]
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# The stm32l1x 384kb have a dual bank flash.
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# Let's add a definition for the second bank here.
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# Add the second flash bank.
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set _FLASHNAME $_CHIPNAME.flash1
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flash bank $_FLASHNAME stm32lx 0x8030000 0 0 0 $_TARGETNAME
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