forked from auracaster/openocd
f2b4897773
The device has compatible flash macro with STM32F1 family, reuse stm32f1x driver code. Detect non-ARM target - for simplicy test target type name 'riscv' and the address has 32 bits. In case of RISC-V CPU use simple chunked write algo - async algo cannot be used as the core implemented in this device doesn't allow memory access while running. Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6704 Tested-by: jenkins Reviewed-by: Tim Newsome <tim@sifive.com>
34 lines
648 B
C
34 lines
648 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <stdint.h>
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#define FLASH_BSY (1 << 0)
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#define FLASH_PGERR (1 << 2)
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#define FLASH_WRPRTERR (1 << 4)
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void flash_write(volatile uint32_t *flash_sr,
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uint32_t hwords_count,
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uint16_t *buffer,
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uint16_t *target_addr) __attribute__((naked));
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void flash_write(volatile uint32_t *flash_sr,
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uint32_t hwords_count,
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uint16_t *buffer,
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uint16_t *target_addr)
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{
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do {
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*target_addr = *buffer++;
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register uint32_t sr;
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do {
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sr = *flash_sr;
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} while (sr & FLASH_BSY);
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if (sr & (FLASH_PGERR | FLASH_WRPRTERR))
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break;
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target_addr++;
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} while (--hwords_count);
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asm("ebreak");
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}
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