forked from auracaster/openocd
2053120ba1
ESP32-S3 is a dual core Xtensa SoC Not full featured yet. Some of the missing functionality: -Semihosting -Flash breakpoints -Flash loader -Apptrace -FreeRTOS Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I44e17088030c96a9be9809f6579a4f16dbfc5794 Reviewed-on: https://review.openocd.org/c/openocd/+/6990 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
32 lines
1016 B
Makefile
32 lines
1016 B
Makefile
# ESP32 Makefile to compile the SoC reset program
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# Copyright (C) 2022 Espressif Systems Ltd.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>
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# Prefix for ESP32 cross compilers (can include a directory path)
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CROSS ?= xtensa-esp32s3-elf-
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APP_ARCH := xtensa
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APP_CHIP := ESP32S3
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APP_CHIP_PATH := $(shell pwd)
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SRCS := $(APP_CHIP_PATH)/esp32s3_cpu_reset_handler.S
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CFLAGS :=
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LDFLAGS :=
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INCLUDES :=
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DEFINES :=
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include ../common.mk
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