forked from auracaster/openocd
23c33e1d3a
When an asynchronous exception occurs at the same time as a breakpoint event (either hardware breakpoint or software breakpoint), it is possible for the processor to halt at the beginning of the exception handler instead of the instruction address pointed by the breakpoint. During debug entry in exception handler state and with BKPT bit set as the only break reason in DFSR, check if there is a breakpoint, which have triggered the debug halt. If there is no such breakpoint, resume execution. The processor services the interrupt and halts again at the correct breakpoint address. The workaround is not needed during target algo run (debug_execution) because interrupts are disabled in PRIMASK register. Also after single step the workaround resume never takes place: the situation is treated as error. Link: https://developer.arm.com/documentation/SDEN1068427/latest/ Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Change-Id: I8b23f39cedd7dccabe7e7066d616fb972b69f769 Reviewed-on: https://review.openocd.org/c/openocd/+/8332 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Liviu Ionescu