forked from auracaster/openocd
04c6a6ee0e
Add configuration files for Espressif RISC-V based chips: - ESP32-C2, ESP32-C3, ESP32-C6, ESP32-H2 target configs - Board configs for builtin USB-JTAG and FTDI interfaces while adding the new config files: - Fix indentation in existing Espressif config files - Adapt esp_common.cfg with RISC-V support - Add explicit 'transport select jtag' to interface configs to avoid 'DEPRECATED: auto-selecting transport' warning Change-Id: I45fcbca2fe50888750e2e98a0a6773de86aad6d0 Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Reviewed-on: https://review.openocd.org/c/openocd/+/9195 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
75 lines
1.8 KiB
INI
75 lines
1.8 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Source the ESP common configuration file.
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source [find target/esp_common.cfg]
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# Target specific global variables
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set _CHIPNAME "esp32s3"
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set _CPUTAPID 0x120034e5
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set _ESP_ARCH "xtensa"
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set _ONLYCPU 3
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set _ESP_SMP_TARGET 1
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set _ESP_SMP_BREAK 1
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set _ESP_EFUSE_MAC_ADDR_REG 0x60007044
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if { [info exists ESP32_S3_ONLYCPU] } {
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set _ONLYCPU $ESP32_S3_ONLYCPU
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}
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proc esp32s3_memprot_is_enabled { } {
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# SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C10C0 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C1124 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C11D0 0] != 0 } {
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return 1
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}
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# IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C10D8 0] != 0 } {
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return 1
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}
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# DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C10FC 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C10E4 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C10F0 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C1104 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C1114 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C119C 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C1248 0] != 0 } {
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return 1
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}
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return 0
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}
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proc esp32s3_soc_reset { } {
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soft_reset_halt
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}
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create_esp_target $_ESP_ARCH
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source [find target/xtensa-core-esp32s3.cfg]
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