auracaster/sw_openocd
3
0
Fork 0
forked from auracaster/openocd
Code Pull Requests Activity
Files
d870ecf5ff4a71e119418fabe8a250a2bab61357
sw_openocd/src/target/riscv
History
Marc Schink d5936dc688 target/riscv: Free registers to avoid memory leak 
Tested with SiFive HiFive1 development board.

Change-Id: I96a9a528057fcf9fc54d3da46a672d2cd54c3d5f
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4885
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-04-10 16:37:21 +01:00
..
asm.h
Add RISC-V support.
2018-07-24 13:07:26 +01:00
batch.c
Lots of RISC-V improvements.
2019-03-27 08:53:09 +00:00
batch.h
Add RISC-V support.
2018-07-24 13:07:26 +01:00
debug_defines.h
Add RISC-V support.
2018-07-24 13:07:26 +01:00
encoding.h
Add RISC-V support.
2018-07-24 13:07:26 +01:00
gdb_regs.h
Add RISC-V support.
2018-07-24 13:07:26 +01:00
Makefile.am
Add RISC-V support.
2018-07-24 13:07:26 +01:00
opcodes.h
Lots of RISC-V improvements.
2019-03-27 08:53:09 +00:00
program.c
Add RISC-V support.
2018-07-24 13:07:26 +01:00
program.h
Lots of RISC-V improvements.
2019-03-27 08:53:09 +00:00
riscv_semihosting.c
Add RISC-V support.
2018-07-24 13:07:26 +01:00
riscv-011.c
Lots of RISC-V improvements.
2019-03-27 08:53:09 +00:00
riscv-013.c
Lots of RISC-V improvements.
2019-03-27 08:53:09 +00:00
riscv.c
target/riscv: Free registers to avoid memory leak
2019-04-10 16:37:21 +01:00
riscv.h
Lots of RISC-V improvements.
2019-03-27 08:53:09 +00:00