forked from auracaster/openocd
5773ff9d82
Some armv8 target have separate i-cache and d-cache. The actual code only handles the flush of the d-cache. Change-Id: I61a223b43c71646bbbed8fa63825360c67700988 Signed-off-by: Adrien Grassein <agrassein@nanoxplore.com> Signed-off-by: Adrien Charruel <acharruel@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8655 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
220 lines
7.1 KiB
C
220 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2015 by pierrr kuo <vichy.kuo@gmail.com>
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*/
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#ifndef OPENOCD_TARGET_ARMV8_OPCODES_H
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#define OPENOCD_TARGET_ARMV8_OPCODES_H
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#include "arm_opcodes.h"
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#define SYSTEM_CUREL_MASK 0xC0
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#define SYSTEM_CUREL_SHIFT 6
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#define SYSTEM_CUREL_EL0 0x0
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#define SYSTEM_CUREL_EL1 0x1
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#define SYSTEM_CUREL_EL2 0x2
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#define SYSTEM_CUREL_EL3 0x3
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#define SYSTEM_CUREL_NONCH 0xF
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#define SYSTEM_AARCH64 0x1
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#define SYSTEM_AAR64_MODE_EL0T 0x0
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#define SYSTEM_AAR64_MODE_EL1T 0x4
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#define SYSTEM_AAR64_MODE_EL1H 0x5
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#define SYSTEM_AAR64_MODE_EL2T 0x8
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#define SYSTEM_AAR64_MODE_EL2H 0x9
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#define SYSTEM_AAR64_MODE_EL3T 0xC
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#define SYSTEM_AAR64_MODE_EL3H 0xd
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#define SYSTEM_DAIF 0xDA11
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#define SYSTEM_DAIF_MASK 0x3C0
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#define SYSTEM_DAIF_SHIFT 6
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#define SYSTEM_ELR_EL1 0xC201
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#define SYSTEM_ELR_EL2 0xE201
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#define SYSTEM_ELR_EL3 0xF201
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#define SYSTEM_SCTLR_EL1 0xC080
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#define SYSTEM_SCTLR_EL2 0xE080
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#define SYSTEM_SCTLR_EL3 0xF080
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#define SYSTEM_FPCR 0xDA20
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#define SYSTEM_FPSR 0xDA21
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#define SYSTEM_DAIF 0xDA11
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#define SYSTEM_NZCV 0xDA10
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#define SYSTEM_SP_EL0 0xC208
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#define SYSTEM_SP_EL1 0xE208
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#define SYSTEM_SP_EL2 0xF208
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#define SYSTEM_SP_SEL 0xC210
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#define SYSTEM_SPSR_ABT 0xE219
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#define SYSTEM_SPSR_FIQ 0xE21B
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#define SYSTEM_SPSR_IRQ 0xE218
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#define SYSTEM_SPSR_UND 0xE21A
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#define SYSTEM_SPSR_EL1 0xC200
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#define SYSTEM_SPSR_EL2 0xE200
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#define SYSTEM_SPSR_EL3 0xF200
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#define SYSTEM_ISR_EL1 0xC608
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#define SYSTEM_DBG_DSPSR_EL0 0xDA28
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#define SYSTEM_DBG_DLR_EL0 0xDA29
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#define SYSTEM_DBG_DTRRX_EL0 0x9828
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#define SYSTEM_DBG_DTRTX_EL0 0x9828
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#define SYSTEM_DBG_DBGDTR_EL0 0x9820
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#define SYSTEM_CCSIDR 0xC800
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#define SYSTEM_CLIDR 0xC801
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#define SYSTEM_CSSELR 0xD000
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#define SYSTEM_CTYPE 0xD801
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#define SYSTEM_CTR 0xD801
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#define SYSTEM_DCCISW 0x43F2
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#define SYSTEM_DCCSW 0x43D2
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#define SYSTEM_ICIVAU 0x5BA9
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/* Attention, SYSTEM_ICIALLU requires rt=0x1f */
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#define SYSTEM_ICIALLU 0x03A8
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#define SYSTEM_DCCVAU 0x5BD9
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#define SYSTEM_DCCIVAC 0x5BF1
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#define SYSTEM_MPIDR 0xC005
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#define SYSTEM_TCR_EL1 0xC102
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#define SYSTEM_TCR_EL2 0xE102
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#define SYSTEM_TCR_EL3 0xF102
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#define SYSTEM_TTBR0_EL1 0xC100
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#define SYSTEM_TTBR0_EL2 0xE100
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#define SYSTEM_TTBR0_EL3 0xF100
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#define SYSTEM_TTBR1_EL1 0xC101
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/* ARMv8 address translation */
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#define SYSTEM_PAR_EL1 0xC3A0
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#define SYSTEM_ATS12E0R 0x63C6
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#define SYSTEM_ATS12E1R 0x63C4
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#define SYSTEM_ATS1E2R 0x63C0
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#define SYSTEM_ATS1E3R 0x73C0
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/* fault status and fault address */
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#define SYSTEM_FAR_EL1 0xC300
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#define SYSTEM_FAR_EL2 0xE300
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#define SYSTEM_FAR_EL3 0xF300
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#define SYSTEM_ESR_EL1 0xC290
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#define SYSTEM_ESR_EL2 0xE290
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#define SYSTEM_ESR_EL3 0xF290
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#define ARMV8_MRS_DSPSR(rt) (0xd53b4500 | (rt))
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#define ARMV8_MSR_DSPSR(rt) (0xd51b4500 | (rt))
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#define ARMV8_MRS_DLR(rt) (0xd53b4520 | (rt))
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#define ARMV8_MSR_DLR(rt) (0xd51b4520 | (rt))
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/* T32 instruction to access coprocessor registers */
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#define ARMV8_MCR_T1(cp, crn, opc1, crm, opc2, rt) ARMV4_5_MCR(cp, opc1, rt, crn, crm, opc2)
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#define ARMV8_MRC_T1(cp, crn, opc1, crm, opc2, rt) ARMV4_5_MRC(cp, opc1, rt, crn, crm, opc2)
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/* T32 instructions to access DSPSR and DLR */
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#define ARMV8_MRC_DSPSR(rt) ARMV8_MRC_T1(15, 4, 3, 5, 0, rt)
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#define ARMV8_MCR_DSPSR(rt) ARMV8_MCR_T1(15, 4, 3, 5, 0, rt)
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#define ARMV8_MRC_DLR(rt) ARMV8_MRC_T1(15, 4, 3, 5, 1, rt)
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#define ARMV8_MCR_DLR(rt) ARMV8_MCR_T1(15, 4, 3, 5, 1, rt)
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#define ARMV8_DCPS1(im) (0xd4a00001 | (((im) & 0xFFFF) << 5))
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#define ARMV8_DCPS2(im) (0xd4a00002 | (((im) & 0xFFFF) << 5))
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#define ARMV8_DCPS3(im) (0xd4a00003 | (((im) & 0xFFFF) << 5))
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#define ARMV8_DCPS(el, im) (0xd4a00000 | (((im) & 0xFFFF) << 5) | el)
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#define ARMV8_DCPS_T1(el) (0xf78f8000 | el)
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#define ARMV8_DRPS 0xd6bf03e0
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#define ARMV8_ERET_T1 0xf3de8f00
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#define ARMV8_DSB_SY 0xd5033F9F
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#define ARMV8_DSB_SY_T1 0xf3bf8f4f
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#define ARMV8_ISB 0xd5033fdf
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#define ARMV8_ISB_SY_T1 0xf3bf8f6f
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#define ARMV8_MRS(system, rt) (0xd5300000 | ((system) << 5) | (rt))
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/* ARM V8 Move to system register. */
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#define ARMV8_MSR_GP(system, rt) \
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(0xd5100000 | ((system) << 5) | (rt))
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/* ARM V8 Move immediate to process state field. */
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#define ARMV8_MSR_IM(op1, crm, op2) \
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(0xd500401f | ((op1) << 16) | ((crm) << 8) | ((op2) << 5))
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#define ARMV8_MRS_T1(r, m1, rd, m) (0xF3E08020 | (r << 20) | (m1 << 16) | (rd << 8) | (m << 4))
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#define ARMV8_MRS_XPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8))
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#define ARMV8_MSR_GP_T1(r, m1, rd, m) (0xF3808020 | (r << 20) | (m1 << 8) | (rd << 16) | (m << 4))
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#define ARMV8_MSR_GP_XPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8))
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#define ARMV8_BKPT(im) (0xD4200000 | ((im & 0xffff) << 5))
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#define ARMV8_HLT(im) (0x0D4400000 | ((im & 0xffff) << 5))
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#define ARMV8_HLT_A1(im) (0xE1000070 | ((im & 0xFFF0) << 4) | (im & 0xF))
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#define ARMV8_HLT_T1(im) (0xba80 | (im & 0x3f))
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#define ARMV8_MOVFSP_64(rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (rt))
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#define ARMV8_MOVTSP_64(rt) ((1 << 31) | 0x11000000 | (rt << 5) | (0x1F))
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#define ARMV8_MOVFSP_32(rt) (0x11000000 | (0x1f << 5) | (rt))
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#define ARMV8_MOVTSP_32(rt) (0x11000000 | (rt << 5) | (0x1F))
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#define ARMV8_LDRB_IP(rd, rn) (0x38401400 | (rn << 5) | rd)
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#define ARMV8_LDRH_IP(rd, rn) (0x78402400 | (rn << 5) | rd)
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#define ARMV8_LDRW_IP(rd, rn) (0xb8404400 | (rn << 5) | rd)
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#define ARMV8_LDRD_IP(rd, rn) (0xf8408400 | (rn << 5) | rd)
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#define ARMV8_LDRB_IP_T3(rd, rn) (0xf8100b01 | (rn << 16) | (rd << 12))
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#define ARMV8_LDRH_IP_T3(rd, rn) (0xf8300b02 | (rn << 16) | (rd << 12))
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#define ARMV8_LDRW_IP_T3(rd, rn) (0xf8500b04 | (rn << 16) | (rd << 12))
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#define ARMV8_STRB_IP(rd, rn) (0x38001400 | (rn << 5) | rd)
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#define ARMV8_STRH_IP(rd, rn) (0x78002400 | (rn << 5) | rd)
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#define ARMV8_STRW_IP(rd, rn) (0xb8004400 | (rn << 5) | rd)
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#define ARMV8_STRD_IP(rd, rn) (0xf8008400 | (rn << 5) | rd)
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#define ARMV8_STRB_IP_T3(rd, rn) (0xf8000b01 | (rn << 16) | (rd << 12))
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#define ARMV8_STRH_IP_T3(rd, rn) (0xf8200b02 | (rn << 16) | (rd << 12))
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#define ARMV8_STRW_IP_T3(rd, rn) (0xf8400b04 | (rn << 16) | (rd << 12))
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#define ARMV8_MOV_GPR_VFP(rd, rn, index) (0x4e083c00 | (index << 20) | (rn << 5) | rd)
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#define ARMV8_MOV_VFP_GPR(rd, rn, index) (0x4e081c00 | (index << 20) | (rn << 5) | rd)
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#define ARMV8_MRS_FPCR(rt) (0xd53b4400 | (rt))
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#define ARMV8_MRS_FPSR(rt) (0xd53b4420 | (rt))
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#define ARMV8_MSR_FPCR(rt) (0xd51b4400 | (rt))
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#define ARMV8_MSR_FPSR(rt) (0xd51b4420 | (rt))
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#define ARMV8_SYS(system, rt) (0xD5080000 | ((system) << 5) | rt)
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enum armv8_opcode {
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READ_REG_CTR,
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READ_REG_CLIDR,
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READ_REG_CSSELR,
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READ_REG_CCSIDR,
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WRITE_REG_CSSELR,
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READ_REG_MPIDR,
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READ_REG_DTRRX,
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WRITE_REG_DTRTX,
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WRITE_REG_DSPSR,
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READ_REG_DSPSR,
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ARMV8_OPC_DSB_SY,
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ARMV8_OPC_DCPS,
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ARMV8_OPC_DRPS,
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ARMV8_OPC_ISB_SY,
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ARMV8_OPC_DCCISW,
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ARMV8_OPC_DCCIVAC,
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ARMV8_OPC_ICIVAU,
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ARMV8_OPC_HLT,
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ARMV8_OPC_STRB_IP,
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ARMV8_OPC_STRH_IP,
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ARMV8_OPC_STRW_IP,
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ARMV8_OPC_STRD_IP,
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ARMV8_OPC_LDRB_IP,
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ARMV8_OPC_LDRH_IP,
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ARMV8_OPC_LDRW_IP,
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ARMV8_OPC_LDRD_IP,
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ARMV8_OPC_ICIALLU,
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ARMV8_OPC_NUM,
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};
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extern uint32_t armv8_opcode(struct armv8_common *armv8, enum armv8_opcode);
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extern void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64);
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#endif /* OPENOCD_TARGET_ARMV8_OPCODES_H */
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