forked from auracaster/openocd
caabdd4a66
The command 'cache auto' was introduced with commit cd440bd32a
("add armv7a_cache handlers") in 2015 to allow disabling the cache
handling done automatically by OpenOCD.
This was probably a way to test the cache handling when there were
still the two independent accesses for APB-AP CPU debug and for
AHB-AP memory bus.
The handling of cache for cortex_a is robust and there is no more
reason to disable it.
The command 'cache auto' is not used in any upstream script.
On target aarch64 this command has never been introduced as the
cache is always handled automatically by OpenOCD.
Drop the command 'cache auto' and add it in the deprecated list.
Drop the flag 'auto_cache_enabled' by considering it as true.
Rename the function 'armv7a_cache_auto_flush_all_data()' as
'armv7a_cache_flush_all_data()' and, while there, fix the error
propagation in SMP case.
Change-Id: I0399f1081b08c4929e0795b76f4a686630f41d56
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8230
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
566 lines
13 KiB
C
566 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* Copyright (C) 2015 by Oleksij Rempel *
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* linux@rempel-privat.de *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "jtag/interface.h"
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#include "arm.h"
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#include "armv7a.h"
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#include "armv7a_cache.h"
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#include <helper/time_support.h>
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#include "arm_opcodes.h"
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#include "smp.h"
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static int armv7a_l1_d_cache_sanity_check(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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if (target->state != TARGET_HALTED) {
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LOG_TARGET_ERROR(target, "not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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/* check that cache data is on at target halt */
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if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) {
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LOG_DEBUG("data cache is not enabled");
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return ERROR_TARGET_INVALID;
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}
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return ERROR_OK;
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}
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static int armv7a_l1_i_cache_sanity_check(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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if (target->state != TARGET_HALTED) {
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LOG_TARGET_ERROR(target, "not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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/* check that cache data is on at target halt */
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if (!armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) {
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LOG_DEBUG("instruction cache is not enabled");
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return ERROR_TARGET_INVALID;
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}
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return ERROR_OK;
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}
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static int armv7a_l1_d_cache_flush_level(struct arm_dpm *dpm, struct armv7a_cachesize *size, int cl)
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{
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int retval = ERROR_OK;
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int32_t c_way, c_index = size->index;
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LOG_DEBUG("cl %" PRId32, cl);
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do {
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keep_alive();
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c_way = size->way;
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do {
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uint32_t value = (c_index << size->index_shift)
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| (c_way << size->way_shift) | (cl << 1);
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/*
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* DCCISW - Clean and invalidate data cache
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* line by Set/Way.
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*/
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
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value);
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if (retval != ERROR_OK)
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goto done;
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c_way -= 1;
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} while (c_way >= 0);
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c_index -= 1;
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} while (c_index >= 0);
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done:
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keep_alive();
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return retval;
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}
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static int armv7a_l1_d_cache_clean_inval_all(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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int cl;
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int retval;
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retval = armv7a_l1_d_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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for (cl = 0; cl < cache->loc; cl++) {
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/* skip i-only caches */
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if (cache->arch[cl].ctype < CACHE_LEVEL_HAS_D_CACHE)
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continue;
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armv7a_l1_d_cache_flush_level(dpm, &cache->arch[cl].d_u_size, cl);
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}
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retval = dpm->finish(dpm);
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return retval;
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done:
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LOG_ERROR("clean invalidate failed");
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dpm->finish(dpm);
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return retval;
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}
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int armv7a_cache_flush_all_data(struct target *target)
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{
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int retval = ERROR_FAIL;
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if (target->smp) {
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struct target_list *head;
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foreach_smp_target(head, target->smp_targets) {
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struct target *curr = head->target;
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if (curr->state == TARGET_HALTED) {
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int retval1 = armv7a_l1_d_cache_clean_inval_all(curr);
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if (retval1 != ERROR_OK)
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retval = retval1;
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}
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}
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} else
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retval = armv7a_l1_d_cache_clean_inval_all(target);
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if (retval != ERROR_OK)
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return retval;
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/* do outer cache flushing after inner caches have been flushed */
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return arm7a_l2x_flush_all_data(target);
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}
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int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
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uint32_t size)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
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uint32_t linelen = armv7a_cache->dminline;
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uint32_t va_line, va_end;
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int retval, i = 0;
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retval = armv7a_l1_d_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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va_line = virt & (-linelen);
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va_end = virt + size;
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/* handle unaligned start */
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if (virt != va_line) {
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/* DCCIMVAC */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line);
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if (retval != ERROR_OK)
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goto done;
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va_line += linelen;
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}
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/* handle unaligned end */
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if ((va_end & (linelen-1)) != 0) {
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va_end &= (-linelen);
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/* DCCIMVAC */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_end);
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if (retval != ERROR_OK)
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goto done;
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}
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while (va_line < va_end) {
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if ((i++ & 0x3f) == 0)
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keep_alive();
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/* DCIMVAC - Invalidate data cache line by VA to PoC. */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 6, 1), va_line);
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if (retval != ERROR_OK)
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goto done;
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va_line += linelen;
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}
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keep_alive();
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dpm->finish(dpm);
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return retval;
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done:
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LOG_ERROR("d-cache invalidate failed");
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keep_alive();
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dpm->finish(dpm);
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return retval;
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}
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int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt,
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unsigned int size)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
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uint32_t linelen = armv7a_cache->dminline;
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uint32_t va_line, va_end;
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int retval, i = 0;
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retval = armv7a_l1_d_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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va_line = virt & (-linelen);
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va_end = virt + size;
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while (va_line < va_end) {
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if ((i++ & 0x3f) == 0)
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keep_alive();
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/* DCCMVAC - Data Cache Clean by MVA to PoC */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 10, 1), va_line);
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if (retval != ERROR_OK)
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goto done;
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va_line += linelen;
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}
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keep_alive();
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dpm->finish(dpm);
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return retval;
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done:
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LOG_ERROR("d-cache invalidate failed");
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keep_alive();
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dpm->finish(dpm);
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return retval;
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}
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int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt,
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unsigned int size)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
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uint32_t linelen = armv7a_cache->dminline;
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uint32_t va_line, va_end;
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int retval, i = 0;
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retval = armv7a_l1_d_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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va_line = virt & (-linelen);
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va_end = virt + size;
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while (va_line < va_end) {
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if ((i++ & 0x3f) == 0)
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keep_alive();
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/* DCCIMVAC */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line);
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if (retval != ERROR_OK)
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goto done;
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va_line += linelen;
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}
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keep_alive();
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dpm->finish(dpm);
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return retval;
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done:
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LOG_ERROR("d-cache invalidate failed");
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keep_alive();
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dpm->finish(dpm);
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return retval;
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}
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int armv7a_l1_i_cache_inval_all(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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int retval;
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retval = armv7a_l1_i_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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if (target->smp) {
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/* ICIALLUIS */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 1, 0), 0);
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} else {
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/* ICIALLU */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 0), 0);
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}
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if (retval != ERROR_OK)
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goto done;
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dpm->finish(dpm);
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return retval;
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done:
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LOG_ERROR("i-cache invalidate failed");
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dpm->finish(dpm);
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return retval;
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}
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int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt,
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uint32_t size)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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struct armv7a_cache_common *armv7a_cache =
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&armv7a->armv7a_mmu.armv7a_cache;
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uint32_t linelen = armv7a_cache->iminline;
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uint32_t va_line, va_end;
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int retval, i = 0;
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retval = armv7a_l1_i_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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va_line = virt & (-linelen);
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va_end = virt + size;
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while (va_line < va_end) {
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if ((i++ & 0x3f) == 0)
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keep_alive();
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/* ICIMVAU - Invalidate instruction cache by VA to PoU. */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 1), va_line);
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if (retval != ERROR_OK)
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goto done;
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/* BPIMVA */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 7), va_line);
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if (retval != ERROR_OK)
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goto done;
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va_line += linelen;
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}
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keep_alive();
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dpm->finish(dpm);
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return retval;
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done:
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LOG_ERROR("i-cache invalidate failed");
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keep_alive();
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dpm->finish(dpm);
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return retval;
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}
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int armv7a_cache_flush_virt(struct target *target, uint32_t virt,
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uint32_t size)
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{
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armv7a_l1_d_cache_flush_virt(target, virt, size);
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armv7a_l2x_cache_flush_virt(target, virt, size);
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return ERROR_OK;
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}
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COMMAND_HANDLER(arm7a_l1_cache_info_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct armv7a_common *armv7a = target_to_armv7a(target);
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return armv7a_handle_cache_info_command(CMD,
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&armv7a->armv7a_mmu.armv7a_cache);
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}
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COMMAND_HANDLER(armv7a_l1_d_cache_clean_inval_all_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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armv7a_l1_d_cache_clean_inval_all(target);
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return 0;
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}
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COMMAND_HANDLER(arm7a_l1_d_cache_inval_virt_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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uint32_t virt, size;
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if (CMD_ARGC == 0 || CMD_ARGC > 2)
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return ERROR_COMMAND_SYNTAX_ERROR;
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|
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if (CMD_ARGC == 2)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
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else
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size = 1;
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
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return armv7a_l1_d_cache_inval_virt(target, virt, size);
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}
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COMMAND_HANDLER(arm7a_l1_d_cache_clean_virt_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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uint32_t virt, size;
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|
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if (CMD_ARGC == 0 || CMD_ARGC > 2)
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return ERROR_COMMAND_SYNTAX_ERROR;
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|
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if (CMD_ARGC == 2)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
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else
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size = 1;
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
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|
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return armv7a_l1_d_cache_clean_virt(target, virt, size);
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}
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|
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COMMAND_HANDLER(armv7a_i_cache_clean_inval_all_cmd)
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{
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struct target *target = get_current_target(CMD_CTX);
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armv7a_l1_i_cache_inval_all(target);
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|
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return 0;
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}
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|
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COMMAND_HANDLER(arm7a_l1_i_cache_inval_virt_cmd)
|
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{
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struct target *target = get_current_target(CMD_CTX);
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uint32_t virt, size;
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|
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if (CMD_ARGC == 0 || CMD_ARGC > 2)
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return ERROR_COMMAND_SYNTAX_ERROR;
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|
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if (CMD_ARGC == 2)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
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else
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size = 1;
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|
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
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return armv7a_l1_i_cache_inval_virt(target, virt, size);
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}
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|
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static const struct command_registration arm7a_l1_d_cache_commands[] = {
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{
|
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.name = "flush_all",
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.handler = armv7a_l1_d_cache_clean_inval_all_cmd,
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.mode = COMMAND_ANY,
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.help = "flush (clean and invalidate) complete l1 d-cache",
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.usage = "",
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},
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{
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.name = "inval",
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.handler = arm7a_l1_d_cache_inval_virt_cmd,
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.mode = COMMAND_ANY,
|
|
.help = "invalidate l1 d-cache by virtual address offset and range size",
|
|
.usage = "<virt_addr> [size]",
|
|
},
|
|
{
|
|
.name = "clean",
|
|
.handler = arm7a_l1_d_cache_clean_virt_cmd,
|
|
.mode = COMMAND_ANY,
|
|
.help = "clean l1 d-cache by virtual address address offset and range size",
|
|
.usage = "<virt_addr> [size]",
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
static const struct command_registration arm7a_l1_i_cache_commands[] = {
|
|
{
|
|
.name = "inval_all",
|
|
.handler = armv7a_i_cache_clean_inval_all_cmd,
|
|
.mode = COMMAND_ANY,
|
|
.help = "invalidate complete l1 i-cache",
|
|
.usage = "",
|
|
},
|
|
{
|
|
.name = "inval",
|
|
.handler = arm7a_l1_i_cache_inval_virt_cmd,
|
|
.mode = COMMAND_ANY,
|
|
.help = "invalidate l1 i-cache by virtual address offset and range size",
|
|
.usage = "<virt_addr> [size]",
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
static const struct command_registration arm7a_l1_di_cache_group_handlers[] = {
|
|
{
|
|
.name = "info",
|
|
.handler = arm7a_l1_cache_info_cmd,
|
|
.mode = COMMAND_ANY,
|
|
.help = "print cache related information",
|
|
.usage = "",
|
|
},
|
|
{
|
|
.name = "d",
|
|
.mode = COMMAND_ANY,
|
|
.help = "l1 d-cache command group",
|
|
.usage = "",
|
|
.chain = arm7a_l1_d_cache_commands,
|
|
},
|
|
{
|
|
.name = "i",
|
|
.mode = COMMAND_ANY,
|
|
.help = "l1 i-cache command group",
|
|
.usage = "",
|
|
.chain = arm7a_l1_i_cache_commands,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
static const struct command_registration arm7a_cache_group_handlers[] = {
|
|
{
|
|
.name = "l1",
|
|
.mode = COMMAND_ANY,
|
|
.help = "l1 cache command group",
|
|
.usage = "",
|
|
.chain = arm7a_l1_di_cache_group_handlers,
|
|
},
|
|
{
|
|
.chain = arm7a_l2x_cache_command_handler,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
const struct command_registration arm7a_cache_command_handlers[] = {
|
|
{
|
|
.name = "cache",
|
|
.mode = COMMAND_ANY,
|
|
.help = "cache command group",
|
|
.usage = "",
|
|
.chain = arm7a_cache_group_handlers,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|