forked from auracaster/openocd
caabdd4a66
The command 'cache auto' was introduced with commit cd440bd32a
("add armv7a_cache handlers") in 2015 to allow disabling the cache
handling done automatically by OpenOCD.
This was probably a way to test the cache handling when there were
still the two independent accesses for APB-AP CPU debug and for
AHB-AP memory bus.
The handling of cache for cortex_a is robust and there is no more
reason to disable it.
The command 'cache auto' is not used in any upstream script.
On target aarch64 this command has never been introduced as the
cache is always handled automatically by OpenOCD.
Drop the command 'cache auto' and add it in the deprecated list.
Drop the flag 'auto_cache_enabled' by considering it as true.
Rename the function 'armv7a_cache_auto_flush_all_data()' as
'armv7a_cache_flush_all_data()' and, while there, fix the error
propagation in SMP case.
Change-Id: I0399f1081b08c4929e0795b76f4a686630f41d56
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8230
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
193 lines
5.1 KiB
C
193 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2009 by David Brownell *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ARMV7A_H
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#define OPENOCD_TARGET_ARMV7A_H
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#include "arm_adi_v5.h"
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#include "armv7a_cache.h"
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#include "arm.h"
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#include "armv4_5_mmu.h"
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#include "armv4_5_cache.h"
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#include "arm_dpm.h"
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enum {
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ARM_PC = 15,
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ARM_CPSR = 16
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};
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#define ARMV7_COMMON_MAGIC 0x0A450999U
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/* VA to PA translation operations opc2 values*/
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#define V2PCWPR 0
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#define V2PCWPW 1
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#define V2PCWUR 2
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#define V2PCWUW 3
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#define V2POWPR 4
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#define V2POWPW 5
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#define V2POWUR 6
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#define V2POWUW 7
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/* L210/L220 cache controller support */
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struct armv7a_l2x_cache {
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uint32_t base;
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uint32_t way;
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};
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struct armv7a_cachesize {
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/* cache dimensioning */
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uint32_t linelen;
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uint32_t associativity;
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uint32_t nsets;
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uint32_t cachesize;
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/* info for set way operation on cache */
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uint32_t index;
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uint32_t index_shift;
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uint32_t way;
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uint32_t way_shift;
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};
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/* information about one architecture cache at any level */
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struct armv7a_arch_cache {
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int ctype; /* cache type, CLIDR encoding */
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struct armv7a_cachesize d_u_size; /* data cache */
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struct armv7a_cachesize i_size; /* instruction cache */
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};
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/* common cache information */
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struct armv7a_cache_common {
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int info; /* -1 invalid, else valid */
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int loc; /* level of coherency */
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uint32_t dminline; /* minimum d-cache linelen */
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uint32_t iminline; /* minimum i-cache linelen */
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struct armv7a_arch_cache arch[6]; /* cache info, L1 - L7 */
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int i_cache_enabled;
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int d_u_cache_enabled;
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/* outer unified cache if some */
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void *outer_cache;
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int (*flush_all_data_cache)(struct target *target);
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};
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struct armv7a_mmu_common {
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/* following field mmu working way */
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int32_t cached; /* 0: not initialized, 1: initialized */
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uint32_t ttbcr; /* cache for ttbcr register */
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uint32_t ttbr[2];
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uint32_t ttbr_mask[2];
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uint32_t ttbr_range[2];
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int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size,
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uint32_t count, uint8_t *buffer);
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struct armv7a_cache_common armv7a_cache;
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uint32_t mmu_enabled;
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};
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struct armv7a_common {
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unsigned int common_magic;
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struct arm arm;
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struct reg_cache *core_cache;
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/* Core Debug Unit */
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struct arm_dpm dpm;
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target_addr_t debug_base;
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struct adiv5_ap *debug_ap;
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/* mdir */
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uint8_t multi_processor_system;
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uint8_t multi_threading_processor;
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uint8_t level2_id;
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uint8_t cluster_id;
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uint8_t cpu_id;
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bool is_armv7r;
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uint32_t rev;
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uint32_t partnum;
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uint32_t arch;
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uint32_t variant;
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uint32_t implementor;
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/* cache specific to V7 Memory Management Unit compatible with v4_5*/
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struct armv7a_mmu_common armv7a_mmu;
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int (*examine_debug_reason)(struct target *target);
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int (*post_debug_entry)(struct target *target);
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void (*pre_restore_context)(struct target *target);
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};
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static inline struct armv7a_common *
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target_to_armv7a(struct target *target)
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{
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return container_of(target->arch_info, struct armv7a_common, arm);
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}
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static inline bool is_armv7a(struct armv7a_common *armv7a)
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{
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return armv7a->common_magic == ARMV7_COMMON_MAGIC;
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}
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/* register offsets from armv7a.debug_base */
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/* See ARMv7a arch spec section C10.2 */
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#define CPUDBG_DIDR 0x000
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/* See ARMv7a arch spec section C10.3 */
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#define CPUDBG_WFAR 0x018
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/* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
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#define CPUDBG_DSCR 0x088
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#define CPUDBG_DRCR 0x090
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#define CPUDBG_PRCR 0x310
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#define CPUDBG_PRSR 0x314
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/* See ARMv7a arch spec section C10.4 */
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#define CPUDBG_DTRRX 0x080
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#define CPUDBG_ITR 0x084
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#define CPUDBG_DTRTX 0x08c
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/* See ARMv7a arch spec section C10.5 */
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#define CPUDBG_BVR_BASE 0x100
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#define CPUDBG_BCR_BASE 0x140
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#define CPUDBG_WVR_BASE 0x180
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#define CPUDBG_WCR_BASE 0x1C0
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#define CPUDBG_VCR 0x01C
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/* See ARMv7a arch spec section C10.6 */
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#define CPUDBG_OSLAR 0x300
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#define CPUDBG_OSLSR 0x304
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#define CPUDBG_OSSRR 0x308
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#define CPUDBG_ECR 0x024
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/* See ARMv7a arch spec section C10.7 */
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#define CPUDBG_DSCCR 0x028
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#define CPUDBG_DSMCR 0x02C
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/* See ARMv7a arch spec section C10.8 */
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#define CPUDBG_AUTHSTATUS 0xFB8
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/* See ARMv7a arch spec DDI 0406C C11.10 */
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#define CPUDBG_ID_PFR1 0xD24
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/* Masks for Vector Catch register */
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#define DBG_VCR_FIQ_MASK ((1 << 31) | (1 << 7))
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#define DBG_VCR_IRQ_MASK ((1 << 30) | (1 << 6))
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#define DBG_VCR_DATA_ABORT_MASK ((1 << 28) | (1 << 4))
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#define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
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#define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2))
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/* Masks for Multiprocessor Affinity Register */
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#define MPIDR_MP_EXT (1UL << 31)
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int armv7a_arch_state(struct target *target);
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int armv7a_identify_cache(struct target *target);
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int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
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int armv7a_handle_cache_info_command(struct command_invocation *cmd,
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struct armv7a_cache_common *armv7a_cache);
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int armv7a_read_ttbcr(struct target *target);
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extern const struct command_registration armv7a_command_handlers[];
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#endif /* OPENOCD_TARGET_ARMV7A_H */
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