forked from auracaster/openocd
fcd7b90db6
This is the first patch intended to make a more precise pracc check when running in legacy mode (code executed by mips32_pracc_exec()). It only makes some cleanups, mostly due to unnecessary code. With the last cache optimizations for processor access (pa for short) all the pracc functions generate the code following some rules that make pa more easily to check: There are no load instructions from dmseg. All the read pas are instruction fetches. PARAM_IN related stuff is not needed. Registers are restored either from COP0 DeSave or from ejtag info fields. PRACC_STACK related stuff is not needed any more. The code starts execution at PRACC_TEXT and there are no branch or jump instruction in the code, apart from the last jump to PRACC_TEXT. The fetch address is ever known. For every store instruction to dmseg the function code sets the address of the write/store pa. The address of every store pa is known. Current code ends execution when reading a second pass through PRACC_TEXT. This approach has same inconveniences: If the code starts in the delay slot of a jump it makes a jump to PRACC_TEXT after executing the first instruction. A second pass through PRACC_TEXt is read and the function exits without any warning. This seems to occur sometimes when a 24kc core is halted in the delay slot of a branch. If a debug mode exception is triggered during the execution of a function the core restarts execution at PRACC_TEXT. Again the function exits without any warning. If for whatever reason the core starts fetching at an unexpected address the code now sends a jump instruction to PRACC_TEXT, but due to the delay slot the core continues fetching at whatever address + 4 and a second jump instruction will be send for execution. The result of a jump instruction in the delay slot of another jump is UNPREDICTABLE. It may work as expected (ar7241), or let the core in the delay slot of a jump to PRACC_TEXT for example. This means the function called next may also fail (pic32mx). Change-Id: I9516a5146ee9c8c694d741331edc7daec9bde4e3 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1825 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
106 lines
4.5 KiB
C
106 lines
4.5 KiB
C
/***************************************************************************
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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* Copyright (C) 2011 by Drasko DRASKOVIC *
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* drasko.draskovic@gmail.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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#ifndef MIPS32_PRACC_H
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#define MIPS32_PRACC_H
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#include <target/mips32.h>
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#include <target/mips_ejtag.h>
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#define MIPS32_PRACC_FASTDATA_AREA 0xFF200000
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#define MIPS32_PRACC_FASTDATA_SIZE 16
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#define MIPS32_PRACC_BASE_ADDR 0xFF200000
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#define MIPS32_PRACC_TEXT 0xFF200200
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#define MIPS32_PRACC_PARAM_OUT 0xFF202000
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#define PRACC_UPPER_BASE_ADDR (MIPS32_PRACC_BASE_ADDR >> 16)
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#define PRACC_OUT_OFFSET (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)
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#define MIPS32_FASTDATA_HANDLER_SIZE 0x80
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#define UPPER16(uint32_t) (uint32_t >> 16)
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#define LOWER16(uint32_t) (uint32_t & 0xFFFF)
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#define NEG16(v) (((~(v)) + 1) & 0xFFFF)
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/*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/
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struct pracc_queue_info {
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int retval;
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const int max_code;
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int code_count;
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int store_count;
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uint32_t *pracc_list; /* Code and store addresses */
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};
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void pracc_queue_init(struct pracc_queue_info *ctx);
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void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr);
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void pracc_queue_free(struct pracc_queue_info *ctx);
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int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info,
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struct pracc_queue_info *ctx, uint32_t *buf);
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int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info,
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uint32_t addr, int size, int count, void *buf);
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int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info,
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uint32_t addr, int size, int count, const void *buf);
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int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
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int write_t, uint32_t addr, int count, uint32_t *buf);
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int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
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int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
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int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_t *code,
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int num_param_out, uint32_t *param_out, int cycle);
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/**
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* \b mips32_cp0_read
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*
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* Simulates mfc0 ASM instruction (Move From C0),
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* i.e. implements copro C0 Register read.
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*
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* @param[in] ejtag_info
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* @param[in] val Storage to hold read value
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* @param[in] cp0_reg Number of copro C0 register we want to read
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* @param[in] cp0_sel Select for the given C0 register
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*
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* @return ERROR_OK on Sucess, ERROR_FAIL otherwise
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*/
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int mips32_cp0_read(struct mips_ejtag *ejtag_info,
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uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel);
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/**
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* \b mips32_cp0_write
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*
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* Simulates mtc0 ASM instruction (Move To C0),
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* i.e. implements copro C0 Register read.
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*
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* @param[in] ejtag_info
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* @param[in] val Value to be written
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* @param[in] cp0_reg Number of copro C0 register we want to write to
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* @param[in] cp0_sel Select for the given C0 register
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*
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* @return ERROR_OK on Sucess, ERROR_FAIL otherwise
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*/
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int mips32_cp0_write(struct mips_ejtag *ejtag_info,
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uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
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#endif
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