135 lines
5.6 KiB
TeX
Executable File
135 lines
5.6 KiB
TeX
Executable File
% !TeX program = lualatex
|
|
\documentclass{muratcan_cv}
|
|
|
|
\setname{Patrick}{Struebin}
|
|
\setaddress{Innsbruck/Austria}
|
|
\setmobile{+4369918284045}
|
|
\setmail{struebin.patrick@gmail.com}
|
|
\setposition{Advanced RD Engineer} %ignored for now
|
|
% \setlinkedinaccount{https://www.linkedin.com} %you can play with color of the template (red is also nice..)
|
|
\setgithubaccount{https://github.com/pstrueb} %you can play with color of the template (red is also nice..)
|
|
\setthemecolor{red} %you can play with color of the template (red is also nice..)
|
|
|
|
\begin{document}
|
|
%Set variables
|
|
%You can add sections, texts, explanations just by copying the style below. Replace the dummy texts "\lipsum[1][x-x]\par" with actual texts.
|
|
%Create header
|
|
\headerview
|
|
\vspace{1ex}
|
|
%Sections
|
|
%
|
|
% Summary
|
|
\addblocktext{Summary}{From my four years of experience in the R\&D of implantable electronics I know how important verification and testing against models and requirements are.
|
|
Testing theories against reality is also a way of thinking that comes naturally with a Science background as a Phycicist.
|
|
During the year of my master thesis and the last four years in the medical industry I did Software development with Python on a daily basis.
|
|
Being in the bussiness of Chochlear-Implant electronics I took parts in multiple implant ASIC development, tapeout and verification cycles.
|
|
Being responsible for Pre- Silicon and also prototype- verification I was able the develop an open source based verification environment (cocotb, ghdl) for the companies implantable ICs.
|
|
I also took part in coneptual devlopment for future fully implantable systems.
|
|
|
|
%5 years of python development experience on a daily basis
|
|
% built a verification framework before
|
|
% lots of experience in testing as required in medical industry
|
|
% multiple tapeouts
|
|
% Know state of the art development methodology (SCRUM)
|
|
% Benefits from CPRE- FL (UML)
|
|
}
|
|
%
|
|
%Education
|
|
\section{Education}
|
|
\datedexperience{LITEF GmbH Freiburg}{2007-2010}
|
|
\explanation{Apprenticeship Electronic technician for devices and systems}
|
|
%\explanationdetail{\coloredbullet\ %
|
|
%\lipsum[1][3-4]\par %replace this part with actual text
|
|
%}
|
|
%
|
|
\datedexperience{"Technische Oberschule" Freiburg}{2010-2012}
|
|
\explanation{Abitur}
|
|
\explanationdetail{
|
|
\coloredbullet\
|
|
Access to univeristy via second-chance education\par
|
|
}
|
|
%
|
|
\datedexperience{University of Innsbruck}{2012-2015}
|
|
\explanation{BSc in Phyics}
|
|
%
|
|
\datedexperience{University of Innsbruck}{2015-2018}
|
|
\explanation{MSc in Phyics}
|
|
\explanationdetail{
|
|
\coloredbullet\ Experimental Applied and ion phyiscs\par
|
|
\coloredbullet\ Lab based Master thesis \href{https://diglib.uibk.ac.at/ulbtirolhs/content/titleinfo/2480047/full.pdf}{Rovibrational state preparation for reactive
|
|
scattering experiments} included development work in Python and C++ \par
|
|
}
|
|
%
|
|
% Experience
|
|
\section{Experience}
|
|
%
|
|
\datedexperience{MED-EL}{2018-2021 / Innsbruck}
|
|
\explanation{R\&D Engineer in Implant electronics}
|
|
\explanationdetail{
|
|
\coloredbullet\ Testsoftware development for prototype implant ASICs\par
|
|
\coloredbullet\ Verification Testing for implant ASICs\par
|
|
\coloredbullet\ Digital Functional Verification simulations in hdl\par
|
|
\coloredbullet\ ASIC concept development for future fully implantable systems \par
|
|
}
|
|
%
|
|
\datedexperience{MED-EL}{2022-Now / Innsbruck}
|
|
\explanation{Advanced R\&D Engineer in Implant electronics}
|
|
\explanationdetail{
|
|
\coloredbullet\ Development and mainenance of an open source based (cocotb, ghdl) hdl verification system for fully implantable ASICs. \par
|
|
\coloredbullet\ Verification Testing for implant ASICs\par
|
|
\coloredbullet\ ASIC concept development for future fully implantable systems \par
|
|
\coloredbullet\ Scrum Master in an transcutaneous implant project\par
|
|
}
|
|
%
|
|
% Skills
|
|
\section{Skills}
|
|
%
|
|
\newcommand{\skillone}{\createskill{Programming Languages}{\textbf{\emph{Advanced:}} \ \ Python \ \
|
|
\textbf{\emph{Intermediate:}} \ \ Labview \cpshalf C \cpshalf C++ \cpshalf \LaTeX \ \ \textbf{\emph{Beginner:}} \ \ SQL
|
|
}}
|
|
%
|
|
\newcommand{\skilltwo}{\createskill{Software Development}{Azure Devops \cpshalf GIT \cpshalf SVN \cpshalf SCRUM Methodology
|
|
}}
|
|
%
|
|
\newcommand{\skillthree}{\createskill{Frameworks \ \& \ Libraries}{\textbf{\emph{Advanced:}} \ \ cocotb \cpshalf NI-DAQmx Python \cpshalf tkinter \cpshalf Matplotplib \cpshalf Numpy \cpshalf \cpshalf Pandas \ \
|
|
}}
|
|
%
|
|
\newcommand{\skillthreecont}{\createskill{}{
|
|
\textbf{\emph{Intermediate:}} qt \cpshalf Scipy \ \ \textbf{\emph{Beginner:}} ROOT Framework
|
|
}}
|
|
%
|
|
\newcommand{\skillfour}{\createskill{Hardware Development}{
|
|
\textbf{\emph{Advanced:}} \ \ NI-daq \ \
|
|
\textbf{\emph{Intermediate:}} \ \ VHDL \cpshalf LTspice \cpshalf Altium Designer \cpshalf Arduino \cpshalf Raspi
|
|
}}
|
|
%
|
|
\newcommand{\skillfourcont}{\createskill{}{
|
|
\textbf{\emph{Beginner:}} \ \ Verilog
|
|
}}
|
|
%
|
|
\newcommand{\skillfive}{\createskill{Languages}{\textbf{\emph{Native:}} \ \ German \ \ \textbf{\emph{Fluent:}} \ \ English \ \ }}
|
|
%
|
|
\createskills{\skillone, \skilltwo, \skillthree, \skillthreecont, \skillfour, \skillfourcont, \skillfive}
|
|
%
|
|
% Experience
|
|
\section{Certificates}
|
|
\newcommand{\extraone}{%
|
|
Professional Scrum Master I\par %replace this part with actual text
|
|
}
|
|
%
|
|
\newcommand{\extratwo}{%
|
|
IREB Certified Professional for Requirements Engineering - Foundation level (CPRE-FL)\par
|
|
}
|
|
%
|
|
% \newcommand{\extrathree}{%
|
|
% \lipsum[1][11-12]%replace this part with actual text
|
|
% }
|
|
%
|
|
\newcommand{\listofextras}{\extraone, \extratwo}
|
|
%
|
|
\createbullets{\listofextras}
|
|
|
|
%Footnote
|
|
\createfootnote
|
|
\end{document}
|