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target/riscv: fix get mode filed for vsatp and hgatp

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Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1258
developed by Mark Zhuang <mark.zhuang@spacemit.com>

Add the necessary get_filed and add a comment to indicate
this section is for VU/VS mode

Change-Id: I898bba6250258c5076a98eb95411fcabccc52b96
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9144
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
This commit is contained in:
Tomas Vanek
2025-05-16 11:06:10 +08:00
parent ffdbdf6b03
commit 18734bcf95
1 changed files with 4 additions and 2 deletions
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6
src/target/riscv/riscv.c
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@@ -3034,6 +3034,8 @@ static int riscv_mmu(struct target *target, bool *enabled)
unsigned int xlen = riscv_xlen(target);
if (v_mode) {
/* In VU or VS mode, MMU is considered enabled when
* either hgatp or vsatp mode is not OFF */
riscv_reg_t vsatp;
if (riscv_reg_get(target, &vsatp, GDB_REGNO_VSATP) != ERROR_OK) {
LOG_TARGET_ERROR(target, "Failed to read vsatp register; priv=0x%" PRIx64,
@@ -3041,7 +3043,7 @@ static int riscv_mmu(struct target *target, bool *enabled)
return ERROR_FAIL;
}
/* vsatp is identical to satp, so we can use the satp macros. */
if (RISCV_SATP_MODE(xlen) != SATP_MODE_OFF) {
if (get_field(vsatp, RISCV_SATP_MODE(xlen)) != SATP_MODE_OFF) {
LOG_TARGET_DEBUG(target, "VS-stage translation is enabled.");
*enabled = true;
return ERROR_OK;
@@ -3053,7 +3055,7 @@ static int riscv_mmu(struct target *target, bool *enabled)
priv);
return ERROR_FAIL;
}
if (RISCV_HGATP_MODE(xlen) != HGATP_MODE_OFF) {
if (get_field(hgatp, RISCV_HGATP_MODE(xlen)) != HGATP_MODE_OFF) {
LOG_TARGET_DEBUG(target, "G-stage address translation is enabled.");
*enabled = true;
} else {