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target/riscv: fix address translation in hypervisor mode

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Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1258
developed by zhefan.lv <zhefan.lv@spacemit.com>

address translation don't need to care hstatus.HU

Change-Id: I40a15ec17347dffaa6e663a637150dfb393471a0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9143
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit is contained in:
Tomas Vanek
2025-05-15 16:32:19 +08:00
parent f5ce311103
commit ffdbdf6b03
1 changed files with 0 additions and 16 deletions
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16
src/target/riscv/riscv.c
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@@ -3034,22 +3034,6 @@ static int riscv_mmu(struct target *target, bool *enabled)
unsigned int xlen = riscv_xlen(target);
if (v_mode) {
/* vsatp and hgatp registers are considered active for the
* purposes of the address-translation algorithm unless the
* effective privilege mode is U and hstatus.HU=0. */
if (effective_mode == PRV_U) {
riscv_reg_t hstatus;
if (riscv_reg_get(target, &hstatus, GDB_REGNO_HSTATUS) != ERROR_OK) {
LOG_TARGET_ERROR(target, "Failed to read hstatus register.");
return ERROR_FAIL;
}
if (get_field(hstatus, HSTATUS_HU) == 0)
/* In hypervisor mode regular satp translation
* doesn't happen. */
return ERROR_OK;
}
riscv_reg_t vsatp;
if (riscv_reg_get(target, &vsatp, GDB_REGNO_VSATP) != ERROR_OK) {
LOG_TARGET_ERROR(target, "Failed to read vsatp register; priv=0x%" PRIx64,