PXA255: force reset config

These chips need both SRST and TRST when debugging,
and SRST doesn't gate JTAG.

tcl/target/pxa255.cfg

@@ -31,6 +31,10 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
 jtag_khz 300
 $_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
 
+# both TRST and SRST are *required* for debug
+# DCSR is often accessed with SRST active
+reset_config trst_and_srst separate srst_nogate
+
 # reset processing that works with PXA
 proc init_reset {mode} {
 	# assert both resets; equivalent to power-on reset