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Merge pull request #52 from riscv/v11_read_without_int

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riscv-v11: Don't perform unexpected operation in cache_write
This commit is contained in:
Megan Wachs
2017-05-25 10:51:27 -07:00
committed by GitHub
parent c431c0eb25 e12f5575ef
commit a1e07e58f4
1 changed files with 1 additions and 1 deletions
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src/target/riscv/riscv-011.c
+1 -1
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@@ -872,7 +872,7 @@ static int cache_write(struct target *target, unsigned int address, bool run)
if (last == info->dramsize) {
// Nothing needs to be written to RAM.
dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | DMCONTROL_INTERRUPT);
dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | (run ? DMCONTROL_INTERRUPT : 0));
} else {
for (unsigned int i = 0; i < info->dramsize; i++) {