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tcl/target: drop more useless reset-start events

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These target configs implement neither device clock setting
nor boost of adapter speed in reset-init event.
Therefore it's not necessary to set back the safe speed in reset-start

Change-Id: I7dcd6f6d1a977388c7a0bc45fe46ede955bd45cb
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9129
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tomas Vanek
2025-09-14 22:40:28 +02:00
committed by Antonio Borneo
parent c168761983
commit a482b78941
6 changed files with 0 additions and 9 deletions
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2
tcl/target/altera_fpgasoc.cfg
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@@ -48,7 +48,6 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80110000
$_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
@@ -56,7 +55,6 @@ $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
#target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
# -coreid 1 -dbgbase 0x80112000
#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
proc cycv_dbginit {target} {

1
tcl/target/imx6.cfg
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@@ -78,6 +78,5 @@ proc imx6_dbginit {target} {
# Slow speed to be sure it will work
adapter speed 1000
$_TARGETNAME configure -event reset-start { adapter speed 1000 }
$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"

3
tcl/target/npcx.cfg
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@@ -46,9 +46,6 @@ $_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE
# 4MHz / 6 = 666KHz, so use 600KHz for it
adapter speed 600
# For safety purposes, set for the lowest cpu clock configuration
$_TARGETNAME configure -event reset-start {adapter speed 600}
# use sysresetreq to perform a system reset
cortex_m reset_config sysresetreq

1
tcl/target/omap3530.cfg
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@@ -66,7 +66,6 @@ proc omap3_dbginit {target} {
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
adapter speed 1000
$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick

1
tcl/target/omapl138.cfg
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@@ -55,7 +55,6 @@ $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
adapter speed 1500
$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable

1
tcl/target/pxa255.cfg
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@@ -31,7 +31,6 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
# Until the PLL kicks in, keep the JTAG clock slow enough
# that we get no errors.
adapter speed 300
$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
# both TRST and SRST are *required* for debug
# DCSR is often accessed with SRST active