target: align switch and case statements
The coding style requires the 'case' to be at the same indentation level of its 'switch' statement. Align the code accordingly. While there: - add space around the operators; - drop useless empty line. Skip all riscv code, as it is going to be updated soon from the external fork. No changes are reported by git log -p -w --ignore-blank-lines --patience Change-Id: I2691dfdd2b6734143e14160b46183623e9773539 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/9051 Tested-by: jenkins
This commit is contained in:
Antonio Borneo
@@ -171,24 +171,23 @@ static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int reg
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uint32_t value_r0, value_r1;
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switch (regnum) {
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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/* move from double word register to r0:r1: "vmov r0, r1, vm"
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* then read r0 via dcc
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*/
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_VMOV(1, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
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((regnum - ARM_VFP_V3_D0) & 0xf)), &value_r0);
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if (retval != ERROR_OK)
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break;
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/* read r1 via dcc */
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retval = dpm->instr_read_data_dcc(dpm,
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ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
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&value_r1);
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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/* move from double word register to r0:r1: "vmov r0, r1, vm"
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* then read r0 via dcc
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*/
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_VMOV(1, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
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((regnum - ARM_VFP_V3_D0) & 0xf)), &value_r0);
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if (retval != ERROR_OK)
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break;
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default:
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break;
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/* read r1 via dcc */
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retval = dpm->instr_read_data_dcc(dpm,
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ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
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&value_r1);
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break;
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default:
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break;
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}
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if (retval == ERROR_OK) {
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@@ -210,54 +209,54 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
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int retval;
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switch (regnum) {
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case 0 ... 14:
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/* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
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retval = dpm->instr_read_data_dcc(dpm,
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ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
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&value);
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break;
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case 15:/* PC
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* "MOV r0, pc"; then return via DCC */
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retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
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case 0 ... 14:
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/* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
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retval = dpm->instr_read_data_dcc(dpm,
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ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
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&value);
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break;
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case 15:/* PC
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* "MOV r0, pc"; then return via DCC */
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retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
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/* NOTE: this seems like a slightly awkward place to update
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* this value ... but if the PC gets written (the only way
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* to change what we compute), the arch spec says subsequent
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* reads return values which are "unpredictable". So this
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* is always right except in those broken-by-intent cases.
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*/
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switch (dpm->arm->core_state) {
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case ARM_STATE_ARM:
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value -= 8;
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break;
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case ARM_STATE_THUMB:
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case ARM_STATE_THUMB_EE:
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value -= 4;
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break;
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case ARM_STATE_JAZELLE:
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/* core-specific ... ? */
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LOG_TARGET_WARNING(dpm->arm->target, "Jazelle PC adjustment unknown");
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break;
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default:
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LOG_TARGET_WARNING(dpm->arm->target, "unknown core state");
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break;
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}
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/* NOTE: this seems like a slightly awkward place to update
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* this value ... but if the PC gets written (the only way
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* to change what we compute), the arch spec says subsequent
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* reads return values which are "unpredictable". So this
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* is always right except in those broken-by-intent cases.
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*/
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switch (dpm->arm->core_state) {
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case ARM_STATE_ARM:
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value -= 8;
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break;
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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return dpm_read_reg_u64(dpm, r, regnum);
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case ARM_VFP_V3_FPSCR:
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/* "VMRS r0, FPSCR"; then return via DCC */
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_VMRS(0), &value);
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case ARM_STATE_THUMB:
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case ARM_STATE_THUMB_EE:
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value -= 4;
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break;
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case ARM_STATE_JAZELLE:
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/* core-specific ... ? */
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LOG_TARGET_WARNING(dpm->arm->target, "Jazelle PC adjustment unknown");
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break;
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default:
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/* 16: "MRS r0, CPSR"; then return via DCC
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* 17: "MRS r0, SPSR"; then return via DCC
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*/
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_MRS(0, regnum & 1),
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&value);
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LOG_TARGET_WARNING(dpm->arm->target, "unknown core state");
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break;
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}
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break;
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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return dpm_read_reg_u64(dpm, r, regnum);
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case ARM_VFP_V3_FPSCR:
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/* "VMRS r0, FPSCR"; then return via DCC */
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_VMRS(0), &value);
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break;
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default:
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/* 16: "MRS r0, CPSR"; then return via DCC
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* 17: "MRS r0, SPSR"; then return via DCC
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*/
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_MRS(0, regnum & 1),
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&value);
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break;
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}
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if (retval == ERROR_OK) {
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@@ -279,24 +278,23 @@ static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int re
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uint32_t value_r1 = buf_get_u32(r->value + 4, 0, 32);
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switch (regnum) {
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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/* write value_r1 to r1 via dcc */
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retval = dpm->instr_write_data_dcc(dpm,
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ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
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value_r1);
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if (retval != ERROR_OK)
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break;
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/* write value_r0 to r0 via dcc then,
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* move to double word register from r0:r1: "vmov vm, r0, r1"
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*/
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_VMOV(0, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
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((regnum - ARM_VFP_V3_D0) & 0xf)), value_r0);
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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/* write value_r1 to r1 via dcc */
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retval = dpm->instr_write_data_dcc(dpm,
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ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
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value_r1);
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if (retval != ERROR_OK)
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break;
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default:
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break;
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/* write value_r0 to r0 via dcc then,
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* move to double word register from r0:r1: "vmov vm, r0, r1"
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*/
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_VMOV(0, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
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((regnum - ARM_VFP_V3_D0) & 0xf)), value_r0);
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break;
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default:
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break;
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}
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if (retval == ERROR_OK) {
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@@ -315,37 +313,37 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum
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uint32_t value = buf_get_u32(r->value, 0, 32);
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switch (regnum) {
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case 0 ... 14:
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/* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
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retval = dpm->instr_write_data_dcc(dpm,
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ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
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value);
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break;
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case 15:/* PC
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* read r0 from DCC; then "MOV pc, r0" */
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retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
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break;
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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return dpm_write_reg_u64(dpm, r, regnum);
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case ARM_VFP_V3_FPSCR:
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/* move to r0 from DCC, then "VMSR FPSCR, r0" */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_VMSR(0), value);
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break;
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default:
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/* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
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* 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
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*/
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
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value);
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if (retval != ERROR_OK)
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return retval;
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case 0 ... 14:
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/* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
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retval = dpm->instr_write_data_dcc(dpm,
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ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
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value);
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break;
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case 15:/* PC
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* read r0 from DCC; then "MOV pc, r0" */
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retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
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break;
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
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return dpm_write_reg_u64(dpm, r, regnum);
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case ARM_VFP_V3_FPSCR:
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/* move to r0 from DCC, then "VMSR FPSCR, r0" */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_VMSR(0), value);
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break;
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default:
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/* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
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* 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
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*/
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
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value);
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if (retval != ERROR_OK)
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return retval;
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if (regnum == 16 && dpm->instr_cpsr_sync)
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retval = dpm->instr_cpsr_sync(dpm);
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if (regnum == 16 && dpm->instr_cpsr_sync)
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retval = dpm->instr_cpsr_sync(dpm);
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break;
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break;
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}
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if (retval == ERROR_OK) {
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@@ -655,24 +653,24 @@ static enum arm_mode dpm_mapmode(struct arm *arm,
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return ARM_MODE_ANY;
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switch (num) {
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/* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
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case 0 ... 7:
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case 15:
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case 16:
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break;
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/* r8..r12 aren't shadowed for anything except FIQ */
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case 8 ... 12:
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if (mode == ARM_MODE_FIQ)
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return mode;
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break;
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/* r13/sp, and r14/lr are always shadowed */
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case 13:
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case 14:
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR:
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/* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
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case 0 ... 7:
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case 15:
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case 16:
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break;
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/* r8..r12 aren't shadowed for anything except FIQ */
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case 8 ... 12:
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if (mode == ARM_MODE_FIQ)
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return mode;
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default:
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LOG_TARGET_WARNING(arm->target, "invalid register #%u", num);
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break;
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break;
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/* r13/sp, and r14/lr are always shadowed */
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case 13:
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case 14:
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case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR:
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return mode;
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default:
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LOG_TARGET_WARNING(arm->target, "invalid register #%u", num);
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break;
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}
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return ARM_MODE_ANY;
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}
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@@ -868,26 +866,26 @@ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
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* v7 hardware, unaligned 4-byte ones too.
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*/
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switch (length) {
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case 1:
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control |= (1 << (addr & 3)) << 5;
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case 1:
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control |= (1 << (addr & 3)) << 5;
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break;
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case 2:
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/* require 2-byte alignment */
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if (!(addr & 1)) {
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control |= (3 << (addr & 2)) << 5;
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break;
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case 2:
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/* require 2-byte alignment */
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if (!(addr & 1)) {
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control |= (3 << (addr & 2)) << 5;
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break;
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}
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/* FALL THROUGH */
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case 4:
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/* require 4-byte alignment */
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if (!(addr & 3)) {
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control |= 0xf << 5;
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break;
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}
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/* FALL THROUGH */
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default:
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LOG_TARGET_ERROR(dpm->arm->target, "unsupported {break,watch}point length/alignment");
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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/* FALL THROUGH */
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case 4:
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/* require 4-byte alignment */
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if (!(addr & 3)) {
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control |= 0xf << 5;
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break;
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}
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/* FALL THROUGH */
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default:
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LOG_TARGET_ERROR(dpm->arm->target, "unsupported {break,watch}point length/alignment");
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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/* other shared control bits:
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@@ -974,15 +972,15 @@ static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t,
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control = dwp->bpwp.control;
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switch (wp->rw) {
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case WPT_READ:
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control |= 1 << 3;
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break;
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case WPT_WRITE:
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control |= 2 << 3;
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break;
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case WPT_ACCESS:
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control |= 3 << 3;
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break;
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case WPT_READ:
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control |= 1 << 3;
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break;
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case WPT_WRITE:
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control |= 2 << 3;
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break;
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case WPT_ACCESS:
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control |= 3 << 3;
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break;
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}
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dwp->bpwp.control = control;
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@@ -1032,17 +1030,17 @@ static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
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void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
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{
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switch (dpm->arm->core_state) {
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case ARM_STATE_ARM:
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addr -= 8;
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break;
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case ARM_STATE_THUMB:
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case ARM_STATE_THUMB_EE:
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addr -= 4;
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break;
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case ARM_STATE_JAZELLE:
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case ARM_STATE_AARCH64:
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/* ?? */
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break;
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case ARM_STATE_ARM:
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addr -= 8;
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break;
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case ARM_STATE_THUMB:
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case ARM_STATE_THUMB_EE:
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addr -= 4;
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break;
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case ARM_STATE_JAZELLE:
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case ARM_STATE_AARCH64:
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/* ?? */
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break;
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}
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dpm->wp_addr = addr;
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}
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@@ -1061,21 +1059,21 @@ void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
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/* Examine debug reason */
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switch (DSCR_ENTRY(dscr)) {
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case DSCR_ENTRY_HALT_REQ: /* HALT request from debugger */
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case DSCR_ENTRY_EXT_DBG_REQ: /* EDBGRQ */
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target->debug_reason = DBG_REASON_DBGRQ;
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break;
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case DSCR_ENTRY_BREAKPOINT: /* HW breakpoint */
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case DSCR_ENTRY_BKPT_INSTR: /* vector catch */
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target->debug_reason = DBG_REASON_BREAKPOINT;
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break;
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case DSCR_ENTRY_IMPRECISE_WATCHPT: /* asynch watchpoint */
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case DSCR_ENTRY_PRECISE_WATCHPT:/* precise watchpoint */
|
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target->debug_reason = DBG_REASON_WATCHPOINT;
|
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break;
|
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default:
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target->debug_reason = DBG_REASON_UNDEFINED;
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break;
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case DSCR_ENTRY_HALT_REQ: /* HALT request from debugger */
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case DSCR_ENTRY_EXT_DBG_REQ: /* EDBGRQ */
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target->debug_reason = DBG_REASON_DBGRQ;
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break;
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case DSCR_ENTRY_BREAKPOINT: /* HW breakpoint */
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case DSCR_ENTRY_BKPT_INSTR: /* vector catch */
|
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target->debug_reason = DBG_REASON_BREAKPOINT;
|
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break;
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case DSCR_ENTRY_IMPRECISE_WATCHPT: /* asynch watchpoint */
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case DSCR_ENTRY_PRECISE_WATCHPT:/* precise watchpoint */
|
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target->debug_reason = DBG_REASON_WATCHPOINT;
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break;
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default:
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target->debug_reason = DBG_REASON_UNDEFINED;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user