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target: align switch and case statements

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The coding style requires the 'case' to be at the same indentation
level of its 'switch' statement.

Align the code accordingly.

While there:
- add space around the operators;
- drop useless empty line.

Skip all riscv code, as it is going to be updated soon from the
external fork.

No changes are reported by
	git log -p -w --ignore-blank-lines --patience

Change-Id: I2691dfdd2b6734143e14160b46183623e9773539
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9051
Tested-by: jenkins
This commit is contained in:
Antonio Borneo
2025-07-26 15:46:26 +02:00
parent 0cd8b6a9d9
commit ddef9cf73b
41 changed files with 4227 additions and 4232 deletions
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48
src/target/aarch64.c
View File

@@ -613,22 +613,22 @@ static int aarch64_restore_one(struct target *target, bool current,
* kill the return address * kill the return address
*/ */
switch (arm->core_state) { switch (arm->core_state) {
case ARM_STATE_ARM: case ARM_STATE_ARM:
resume_pc &= 0xFFFFFFFC; resume_pc &= 0xFFFFFFFC;
break; break;
case ARM_STATE_AARCH64: case ARM_STATE_AARCH64:
resume_pc &= 0xFFFFFFFFFFFFFFFCULL; resume_pc &= 0xFFFFFFFFFFFFFFFCULL;
break; break;
case ARM_STATE_THUMB: case ARM_STATE_THUMB:
case ARM_STATE_THUMB_EE: case ARM_STATE_THUMB_EE:
/* When the return address is loaded into PC /* When the return address is loaded into PC
* bit 0 must be 1 to stay in Thumb state * bit 0 must be 1 to stay in Thumb state
*/ */
resume_pc |= 0x1; resume_pc |= 0x1;
break; break;
case ARM_STATE_JAZELLE: case ARM_STATE_JAZELLE:
LOG_ERROR("How do I resume into Jazelle state??"); LOG_ERROR("How do I resume into Jazelle state??");
return ERROR_FAIL; return ERROR_FAIL;
} }
LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc); LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc);
buf_set_u64(arm->pc->value, 0, 64, resume_pc); buf_set_u64(arm->pc->value, 0, 64, resume_pc);
@@ -3026,14 +3026,14 @@ COMMAND_HANDLER(aarch64_handle_disassemble_command)
target_addr_t address; target_addr_t address;
switch (CMD_ARGC) { switch (CMD_ARGC) {
case 2: case 2:
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count); COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
/* FALL THROUGH */ /* FALL THROUGH */
case 1: case 1:
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address); COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
return a64_disassemble(CMD, target, address, count); return a64_disassemble(CMD, target, address, count);

24
src/target/arc.c
View File

@@ -1892,18 +1892,18 @@ static int arc_set_watchpoint(struct target *target,
int enable = AP_AC_TT_DISABLE; int enable = AP_AC_TT_DISABLE;
switch (watchpoint->rw) { switch (watchpoint->rw) {
case WPT_READ: case WPT_READ:
enable = AP_AC_TT_READ; enable = AP_AC_TT_READ;
break; break;
case WPT_WRITE: case WPT_WRITE:
enable = AP_AC_TT_WRITE; enable = AP_AC_TT_WRITE;
break; break;
case WPT_ACCESS: case WPT_ACCESS:
enable = AP_AC_TT_READWRITE; enable = AP_AC_TT_READWRITE;
break; break;
default: default:
LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access"); LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access");
return ERROR_FAIL; return ERROR_FAIL;
} }
int retval = arc_configure_actionpoint(target, wp_num, int retval = arc_configure_actionpoint(target, wp_num,

46
src/target/arc_cmd.c
View File

@@ -709,29 +709,29 @@ COMMAND_HANDLER(arc_handle_get_reg_field)
int retval = arc_reg_get_field(target, reg_name, field_name, &value); int retval = arc_reg_get_field(target, reg_name, field_name, &value);
switch (retval) { switch (retval) {
case ERROR_OK: case ERROR_OK:
break; break;
case ERROR_ARC_REGISTER_NOT_FOUND: case ERROR_ARC_REGISTER_NOT_FOUND:
command_print(CMD, command_print(CMD,
"Register `%s' has not been found.", reg_name); "Register `%s' has not been found.", reg_name);
return ERROR_COMMAND_ARGUMENT_INVALID; return ERROR_COMMAND_ARGUMENT_INVALID;
case ERROR_ARC_REGISTER_IS_NOT_STRUCT: case ERROR_ARC_REGISTER_IS_NOT_STRUCT:
command_print(CMD, command_print(CMD,
"Register `%s' must have 'struct' type.", reg_name); "Register `%s' must have 'struct' type.", reg_name);
return ERROR_COMMAND_ARGUMENT_INVALID; return ERROR_COMMAND_ARGUMENT_INVALID;
case ERROR_ARC_REGISTER_FIELD_NOT_FOUND: case ERROR_ARC_REGISTER_FIELD_NOT_FOUND:
command_print(CMD, command_print(CMD,
"Field `%s' has not been found in register `%s'.", "Field `%s' has not been found in register `%s'.",
field_name, reg_name); field_name, reg_name);
return ERROR_COMMAND_ARGUMENT_INVALID; return ERROR_COMMAND_ARGUMENT_INVALID;
case ERROR_ARC_FIELD_IS_NOT_BITFIELD: case ERROR_ARC_FIELD_IS_NOT_BITFIELD:
command_print(CMD, command_print(CMD,
"Field `%s' is not a 'bitfield' field in a structure.", "Field `%s' is not a 'bitfield' field in a structure.",
field_name); field_name);
return ERROR_COMMAND_ARGUMENT_INVALID; return ERROR_COMMAND_ARGUMENT_INVALID;
default: default:
/* Pass through other errors. */ /* Pass through other errors. */
return retval; return retval;
} }
command_print(CMD, "0x%" PRIx32, value); command_print(CMD, "0x%" PRIx32, value);

212
src/target/arm11.c
View File

@@ -414,19 +414,19 @@ static uint32_t arm11_nextpc(struct arm11_common *arm11, bool current,
* kill the return address * kill the return address
*/ */
switch (arm11->arm.core_state) { switch (arm11->arm.core_state) {
case ARM_STATE_ARM: case ARM_STATE_ARM:
address &= 0xFFFFFFFC; address &= 0xFFFFFFFC;
break; break;
case ARM_STATE_THUMB: case ARM_STATE_THUMB:
/* When the return address is loaded into PC /* When the return address is loaded into PC
* bit 0 must be 1 to stay in Thumb state * bit 0 must be 1 to stay in Thumb state
*/ */
address |= 0x1; address |= 0x1;
break; break;
/* catch-all for JAZELLE and THUMB_EE */ /* catch-all for JAZELLE and THUMB_EE */
default: default:
break; break;
} }
buf_set_u32(value, 0, 32, address); buf_set_u32(value, 0, 32, address);
@@ -819,44 +819,44 @@ static int arm11_read_memory_inner(struct target *target,
return retval; return retval;
switch (size) { switch (size) {
case 1: case 1:
arm11->arm.core_cache->reg_list[1].dirty = true; arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++) { for (size_t i = 0; i < count; i++) {
/* ldrb r1, [r0], #1 */ /* ldrb r1, [r0], #1 */
/* ldrb r1, [r0] */ /* ldrb r1, [r0] */
CHECK_RETVAL(arm11_run_instr_no_data1(arm11, CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000)); !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
uint32_t res; uint32_t res;
/* MCR p14,0,R1,c0,c5,0 */ /* MCR p14,0,R1,c0,c5,0 */
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
*buffer++ = res; *buffer++ = res;
} }
break; break;
case 2: case 2:
arm11->arm.core_cache->reg_list[1].dirty = true; arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++) { for (size_t i = 0; i < count; i++) {
/* ldrh r1, [r0], #2 */ /* ldrh r1, [r0], #2 */
CHECK_RETVAL(arm11_run_instr_no_data1(arm11, CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0)); !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
uint32_t res; uint32_t res;
/* MCR p14,0,R1,c0,c5,0 */ /* MCR p14,0,R1,c0,c5,0 */
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
uint16_t svalue = res; uint16_t svalue = res;
memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t)); memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
} }
break; break;
case 4: case 4:
{ {
uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00; uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
@@ -925,52 +925,52 @@ static int arm11_write_memory_inner(struct target *target,
bool burst = arm11->memwrite_burst && (count > 1); bool burst = arm11->memwrite_burst && (count > 1);
switch (size) { switch (size) {
case 1: case 1:
arm11->arm.core_cache->reg_list[1].dirty = true; arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++) { for (size_t i = 0; i < count; i++) {
/* load r1 from DCC with byte data */ /* load r1 from DCC with byte data */
/* MRC p14,0,r1,c0,c5,0 */ /* MRC p14,0,r1,c0,c5,0 */
retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++); retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
/* write r1 to memory */ /* write r1 to memory */
/* strb r1, [r0], #1 */ /* strb r1, [r0], #1 */
/* strb r1, [r0] */ /* strb r1, [r0] */
retval = arm11_run_instr_no_data1(arm11, retval = arm11_run_instr_no_data1(arm11,
!no_increment ? 0xe4c01001 : 0xe5c01000); !no_increment ? 0xe4c01001 : 0xe5c01000);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
} }
break; break;
case 2: case 2:
arm11->arm.core_cache->reg_list[1].dirty = true; arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++) { for (size_t i = 0; i < count; i++) {
uint16_t value; uint16_t value;
memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t)); memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
/* load r1 from DCC with halfword data */ /* load r1 from DCC with halfword data */
/* MRC p14,0,r1,c0,c5,0 */ /* MRC p14,0,r1,c0,c5,0 */
retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value); retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
/* write r1 to memory */ /* write r1 to memory */
/* strh r1, [r0], #2 */ /* strh r1, [r0], #2 */
/* strh r1, [r0] */ /* strh r1, [r0] */
retval = arm11_run_instr_no_data1(arm11, retval = arm11_run_instr_no_data1(arm11,
!no_increment ? 0xe0c010b2 : 0xe1c010b0); !no_increment ? 0xe0c010b2 : 0xe1c010b0);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
} }
break; break;
case 4: case 4:
{ {
/* stream word data through DCC directly to memory */ /* stream word data through DCC directly to memory */
/* increment: STC p14,c5,[R0],#4 */ /* increment: STC p14,c5,[R0],#4 */
@@ -1159,34 +1159,34 @@ static int arm11_examine(struct target *target)
/* assume the manufacturer id is ok; check the part # */ /* assume the manufacturer id is ok; check the part # */
switch ((device_id >> 12) & 0xFFFF) { switch ((device_id >> 12) & 0xFFFF) {
case 0x7B36: case 0x7B36:
type = "ARM1136"; type = "ARM1136";
break; break;
case 0x7B37: case 0x7B37:
type = "ARM11 MPCore"; type = "ARM11 MPCore";
break; break;
case 0x7B56: case 0x7B56:
type = "ARM1156"; type = "ARM1156";
break; break;
case 0x7B76: case 0x7B76:
arm11->arm.core_type = ARM_CORE_TYPE_SEC_EXT; arm11->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
/* NOTE: could default arm11->hardware_step to true */ /* NOTE: could default arm11->hardware_step to true */
type = "ARM1176"; type = "ARM1176";
break; break;
default: default:
LOG_ERROR("unexpected ARM11 ID code"); LOG_ERROR("unexpected ARM11 ID code");
return ERROR_FAIL; return ERROR_FAIL;
} }
LOG_INFO("found %s", type); LOG_INFO("found %s", type);
/* unlikely this could ever fail, but ... */ /* unlikely this could ever fail, but ... */
switch ((didr >> 16) & 0x0F) { switch ((didr >> 16) & 0x0F) {
case ARM11_DEBUG_V6: case ARM11_DEBUG_V6:
case ARM11_DEBUG_V61: /* supports security extensions */ case ARM11_DEBUG_V61: /* supports security extensions */
break; break;
default: default:
LOG_ERROR("Only ARM v6 and v6.1 debug supported."); LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
return ERROR_FAIL; return ERROR_FAIL;
} }
arm11->brp = ((didr >> 24) & 0x0F) + 1; arm11->brp = ((didr >> 24) & 0x0F) + 1;
@@ -1250,13 +1250,13 @@ COMMAND_HANDLER(arm11_handle_vcr)
struct arm11_common *arm11 = target_to_arm11(target); struct arm11_common *arm11 = target_to_arm11(target);
switch (CMD_ARGC) { switch (CMD_ARGC) {
case 0: case 0:
break; break;
case 1: case 1:
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr);
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
LOG_INFO("VCR 0x%08" PRIx32, arm11->vcr); LOG_INFO("VCR 0x%08" PRIx32, arm11->vcr);

88
src/target/arm11_dbgtap.c
View File

@@ -85,30 +85,30 @@ static const char *arm11_ir_to_string(uint8_t ir)
const char *s = "unknown"; const char *s = "unknown";
switch (ir) { switch (ir) {
case ARM11_EXTEST: case ARM11_EXTEST:
s = "EXTEST"; s = "EXTEST";
break; break;
case ARM11_SCAN_N: case ARM11_SCAN_N:
s = "SCAN_N"; s = "SCAN_N";
break; break;
case ARM11_RESTART: case ARM11_RESTART:
s = "RESTART"; s = "RESTART";
break; break;
case ARM11_HALT: case ARM11_HALT:
s = "HALT"; s = "HALT";
break; break;
case ARM11_INTEST: case ARM11_INTEST:
s = "INTEST"; s = "INTEST";
break; break;
case ARM11_ITRSEL: case ARM11_ITRSEL:
s = "ITRSEL"; s = "ITRSEL";
break; break;
case ARM11_IDCODE: case ARM11_IDCODE:
s = "IDCODE"; s = "IDCODE";
break; break;
case ARM11_BYPASS: case ARM11_BYPASS:
s = "BYPASS"; s = "BYPASS";
break; break;
} }
return s; return s;
} }
@@ -1061,17 +1061,17 @@ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t,
action[1].value = control; action[1].value = control;
switch (index_t) { switch (index_t) {
case 0 ... 15: case 0 ... 15:
action[0].address = ARM11_SC7_BVR0 + index_t; action[0].address = ARM11_SC7_BVR0 + index_t;
action[1].address = ARM11_SC7_BCR0 + index_t; action[1].address = ARM11_SC7_BCR0 + index_t;
break; break;
case 16 ... 32: case 16 ... 32:
index_t -= 16; index_t -= 16;
action[0].address = ARM11_SC7_WVR0 + index_t; action[0].address = ARM11_SC7_WVR0 + index_t;
action[1].address = ARM11_SC7_WCR0 + index_t; action[1].address = ARM11_SC7_WCR0 + index_t;
break; break;
default: default:
return ERROR_FAIL; return ERROR_FAIL;
} }
arm11->bpwp_n += 2; arm11->bpwp_n += 2;
@@ -1090,15 +1090,15 @@ static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
action[0].value = 0; action[0].value = 0;
switch (index_t) { switch (index_t) {
case 0 ... 15: case 0 ... 15:
action[0].address = ARM11_SC7_BCR0 + index_t; action[0].address = ARM11_SC7_BCR0 + index_t;
break; break;
case 16 ... 32: case 16 ... 32:
index_t -= 16; index_t -= 16;
action[0].address = ARM11_SC7_WCR0 + index_t; action[0].address = ARM11_SC7_WCR0 + index_t;
break; break;
default: default:
return ERROR_FAIL; return ERROR_FAIL;
} }
arm11->bpwp_n += 1; arm11->bpwp_n += 1;

336
src/target/arm7_9_common.c
View File

@@ -2136,18 +2136,48 @@ int arm7_9_read_memory(struct target *target,
arm7_9->write_core_regs(target, 0x1, reg); arm7_9->write_core_regs(target, 0x1, reg);
switch (size) { switch (size) {
case 4: case 4:
while (num_accesses < count) { while (num_accesses < count) {
uint32_t reg_list; uint32_t reg_list;
thisrun_accesses = thisrun_accesses =
((count - num_accesses) >= 14) ? 14 : (count - num_accesses); ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
if (last_reg <= thisrun_accesses) if (last_reg <= thisrun_accesses)
last_reg = thisrun_accesses; last_reg = thisrun_accesses;
arm7_9->load_word_regs(target, reg_list); arm7_9->load_word_regs(target, reg_list);
/* fast memory reads are only safe when the target is running
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
retval = arm7_9_execute_sys_speed(target);
if (retval != ERROR_OK)
return retval;
arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
/* advance buffer, count number of accesses */
buffer += thisrun_accesses * 4;
num_accesses += thisrun_accesses;
keep_alive();
}
break;
case 2:
while (num_accesses < count) {
uint32_t reg_list;
thisrun_accesses =
((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
for (i = 1; i <= thisrun_accesses; i++) {
if (i > last_reg)
last_reg = i;
arm7_9->load_hword_reg(target, i);
/* fast memory reads are only safe when the target is running /* fast memory reads are only safe when the target is running
* from a sufficiently high clock (32 kHz is usually too slow) * from a sufficiently high clock (32 kHz is usually too slow)
*/ */
@@ -2158,78 +2188,48 @@ int arm7_9_read_memory(struct target *target,
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
/* advance buffer, count number of accesses */
buffer += thisrun_accesses * 4;
num_accesses += thisrun_accesses;
keep_alive();
} }
break;
case 2:
while (num_accesses < count) {
uint32_t reg_list;
thisrun_accesses =
((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
for (i = 1; i <= thisrun_accesses; i++) { arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
if (i > last_reg)
last_reg = i;
arm7_9->load_hword_reg(target, i);
/* fast memory reads are only safe when the target is running
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
retval = arm7_9_execute_sys_speed(target);
if (retval != ERROR_OK)
return retval;
} /* advance buffer, count number of accesses */
buffer += thisrun_accesses * 2;
num_accesses += thisrun_accesses;
arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2); keep_alive();
}
break;
case 1:
while (num_accesses < count) {
uint32_t reg_list;
thisrun_accesses =
((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
/* advance buffer, count number of accesses */ for (i = 1; i <= thisrun_accesses; i++) {
buffer += thisrun_accesses * 2; if (i > last_reg)
num_accesses += thisrun_accesses; last_reg = i;
arm7_9->load_byte_reg(target, i);
keep_alive(); /* fast memory reads are only safe when the target is running
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
retval = arm7_9_execute_sys_speed(target);
if (retval != ERROR_OK)
return retval;
} }
break;
case 1:
while (num_accesses < count) {
uint32_t reg_list;
thisrun_accesses =
((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
for (i = 1; i <= thisrun_accesses; i++) { arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
if (i > last_reg)
last_reg = i;
arm7_9->load_byte_reg(target, i);
/* fast memory reads are only safe when the target is running
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
retval = arm7_9_execute_sys_speed(target);
if (retval != ERROR_OK)
return retval;
}
arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1); /* advance buffer, count number of accesses */
buffer += thisrun_accesses * 1;
num_accesses += thisrun_accesses;
/* advance buffer, count number of accesses */ keep_alive();
buffer += thisrun_accesses * 1; }
num_accesses += thisrun_accesses; break;
keep_alive();
}
break;
} }
if (!is_arm_mode(arm->core_mode)) if (!is_arm_mode(arm->core_mode))
@@ -2308,23 +2308,67 @@ int arm7_9_write_memory(struct target *target,
embeddedice_store_reg(dbg_ctrl); embeddedice_store_reg(dbg_ctrl);
switch (size) { switch (size) {
case 4: case 4:
while (num_accesses < count) { while (num_accesses < count) {
uint32_t reg_list; uint32_t reg_list;
thisrun_accesses = thisrun_accesses =
((count - num_accesses) >= 14) ? 14 : (count - num_accesses); ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
for (i = 1; i <= thisrun_accesses; i++) { for (i = 1; i <= thisrun_accesses; i++) {
if (i > last_reg) if (i > last_reg)
last_reg = i; last_reg = i;
reg[i] = target_buffer_get_u32(target, buffer); reg[i] = target_buffer_get_u32(target, buffer);
buffer += 4; buffer += 4;
} }
arm7_9->write_core_regs(target, reg_list, reg); arm7_9->write_core_regs(target, reg_list, reg);
arm7_9->store_word_regs(target, reg_list); arm7_9->store_word_regs(target, reg_list);
/* fast memory writes are only safe when the target is running
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access) {
retval = arm7_9_execute_fast_sys_speed(target);
} else {
retval = arm7_9_execute_sys_speed(target);
/*
* if memory writes are made when the clock is running slow
* (i.e. 32 kHz) which is necessary in some scripts to reconfigure
* processor operations after a "reset halt" or "reset init",
* need to immediately stroke the keep alive or will end up with
* gdb "keep alive not sent error message" problem.
*/
keep_alive();
}
if (retval != ERROR_OK)
return retval;
num_accesses += thisrun_accesses;
}
break;
case 2:
while (num_accesses < count) {
uint32_t reg_list;
thisrun_accesses =
((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
for (i = 1; i <= thisrun_accesses; i++) {
if (i > last_reg)
last_reg = i;
reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
buffer += 2;
}
arm7_9->write_core_regs(target, reg_list, reg);
for (i = 1; i <= thisrun_accesses; i++) {
arm7_9->store_hword_reg(target, i);
/* fast memory writes are only safe when the target is running /* fast memory writes are only safe when the target is running
* from a sufficiently high clock (32 kHz is usually too slow) * from a sufficiently high clock (32 kHz is usually too slow)
@@ -2347,99 +2391,55 @@ int arm7_9_write_memory(struct target *target,
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
num_accesses += thisrun_accesses;
} }
break;
case 2:
while (num_accesses < count) {
uint32_t reg_list;
thisrun_accesses =
((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
for (i = 1; i <= thisrun_accesses; i++) { num_accesses += thisrun_accesses;
if (i > last_reg) }
last_reg = i; break;
reg[i] = target_buffer_get_u16(target, buffer) & 0xffff; case 1:
buffer += 2; while (num_accesses < count) {
} uint32_t reg_list;
thisrun_accesses =
((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
arm7_9->write_core_regs(target, reg_list, reg); for (i = 1; i <= thisrun_accesses; i++) {
if (i > last_reg)
last_reg = i;
reg[i] = *buffer++ & 0xff;
}
for (i = 1; i <= thisrun_accesses; i++) { arm7_9->write_core_regs(target, reg_list, reg);
arm7_9->store_hword_reg(target, i);
/* fast memory writes are only safe when the target is running for (i = 1; i <= thisrun_accesses; i++) {
* from a sufficiently high clock (32 kHz is usually too slow) arm7_9->store_byte_reg(target, i);
/* fast memory writes are only safe when the target is running
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access) {
retval = arm7_9_execute_fast_sys_speed(target);
} else {
retval = arm7_9_execute_sys_speed(target);
/*
* if memory writes are made when the clock is running slow
* (i.e. 32 kHz) which is necessary in some scripts to reconfigure
* processor operations after a "reset halt" or "reset init",
* need to immediately stroke the keep alive or will end up with
* gdb "keep alive not sent error message" problem.
*/ */
if (arm7_9->fast_memory_access) {
retval = arm7_9_execute_fast_sys_speed(target);
} else {
retval = arm7_9_execute_sys_speed(target);
/* keep_alive();
* if memory writes are made when the clock is running slow
* (i.e. 32 kHz) which is necessary in some scripts to reconfigure
* processor operations after a "reset halt" or "reset init",
* need to immediately stroke the keep alive or will end up with
* gdb "keep alive not sent error message" problem.
*/
keep_alive();
}
if (retval != ERROR_OK)
return retval;
} }
num_accesses += thisrun_accesses; if (retval != ERROR_OK)
return retval;
} }
break;
case 1:
while (num_accesses < count) {
uint32_t reg_list;
thisrun_accesses =
((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
for (i = 1; i <= thisrun_accesses; i++) { num_accesses += thisrun_accesses;
if (i > last_reg) }
last_reg = i; break;
reg[i] = *buffer++ & 0xff;
}
arm7_9->write_core_regs(target, reg_list, reg);
for (i = 1; i <= thisrun_accesses; i++) {
arm7_9->store_byte_reg(target, i);
/* fast memory writes are only safe when the target is running
* from a sufficiently high clock (32 kHz is usually too slow)
*/
if (arm7_9->fast_memory_access) {
retval = arm7_9_execute_fast_sys_speed(target);
} else {
retval = arm7_9_execute_sys_speed(target);
/*
* if memory writes are made when the clock is running slow
* (i.e. 32 kHz) which is necessary in some scripts to reconfigure
* processor operations after a "reset halt" or "reset init",
* need to immediately stroke the keep alive or will end up with
* gdb "keep alive not sent error message" problem.
*/
keep_alive();
}
if (retval != ERROR_OK)
return retval;
}
num_accesses += thisrun_accesses;
}
break;
} }
/* Re-Set DBGACK */ /* Re-Set DBGACK */

18
src/target/arm7tdmi.c
View File

@@ -327,15 +327,15 @@ static void arm7tdmi_read_core_regs_target_buffer(struct target *target,
/* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */ /* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */
if (mask & (1 << i)) { if (mask & (1 << i)) {
switch (size) { switch (size) {
case 4: case 4:
arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
break; break;
case 2: case 2:
arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
break; break;
case 1: case 1:
arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
break; break;
} }
} }
} }

156
src/target/arm926ejs.c
View File

@@ -221,88 +221,88 @@ static int arm926ejs_examine_debug_reason(struct target *target)
debug_reason = buf_get_u32(dbg_stat->value, 6, 4); debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
switch (debug_reason) { switch (debug_reason) {
case 0: case 0:
LOG_DEBUG("no *NEW* debug entry (?missed one?)"); LOG_DEBUG("no *NEW* debug entry (?missed one?)");
/* ... since last restart or debug reset ... */ /* ... since last restart or debug reset ... */
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
break; break;
case 1: case 1:
LOG_DEBUG("breakpoint from EICE unit 0"); LOG_DEBUG("breakpoint from EICE unit 0");
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
break; break;
case 2: case 2:
LOG_DEBUG("breakpoint from EICE unit 1"); LOG_DEBUG("breakpoint from EICE unit 1");
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
break; break;
case 3: case 3:
LOG_DEBUG("soft breakpoint (BKPT instruction)"); LOG_DEBUG("soft breakpoint (BKPT instruction)");
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
break; break;
case 4: case 4:
LOG_DEBUG("vector catch breakpoint"); LOG_DEBUG("vector catch breakpoint");
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
break; break;
case 5: case 5:
LOG_DEBUG("external breakpoint"); LOG_DEBUG("external breakpoint");
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
break; break;
case 6: case 6:
LOG_DEBUG("watchpoint from EICE unit 0"); LOG_DEBUG("watchpoint from EICE unit 0");
target->debug_reason = DBG_REASON_WATCHPOINT; target->debug_reason = DBG_REASON_WATCHPOINT;
break; break;
case 7: case 7:
LOG_DEBUG("watchpoint from EICE unit 1"); LOG_DEBUG("watchpoint from EICE unit 1");
target->debug_reason = DBG_REASON_WATCHPOINT; target->debug_reason = DBG_REASON_WATCHPOINT;
break; break;
case 8: case 8:
LOG_DEBUG("external watchpoint"); LOG_DEBUG("external watchpoint");
target->debug_reason = DBG_REASON_WATCHPOINT; target->debug_reason = DBG_REASON_WATCHPOINT;
break; break;
case 9: case 9:
LOG_DEBUG("internal debug request"); LOG_DEBUG("internal debug request");
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
break; break;
case 10: case 10:
LOG_DEBUG("external debug request"); LOG_DEBUG("external debug request");
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
break; break;
case 11: case 11:
LOG_DEBUG("debug re-entry from system speed access"); LOG_DEBUG("debug re-entry from system speed access");
/* This is normal when connecting to something that's /* This is normal when connecting to something that's
* already halted, or in some related code paths, but * already halted, or in some related code paths, but
* otherwise is surprising (and presumably wrong). * otherwise is surprising (and presumably wrong).
*/ */
switch (target->debug_reason) { switch (target->debug_reason) {
case DBG_REASON_DBGRQ: case DBG_REASON_DBGRQ:
break;
default:
LOG_ERROR("unexpected -- debug re-entry");
/* FALLTHROUGH */
case DBG_REASON_UNDEFINED:
target->debug_reason = DBG_REASON_DBGRQ;
break;
}
break;
case 12:
/* FIX!!!! here be dragons!!! We need to fail here so
* the target will interpreted as halted but we won't
* try to talk to it right now... a resume + halt seems
* to sync things up again. Please send an email to
* openocd development mailing list if you have hardware
* to donate to look into this problem....
*/
LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
target->debug_reason = DBG_REASON_DBGRQ;
break; break;
default: default:
LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason); LOG_ERROR("unexpected -- debug re-entry");
/* Oh agony! should we interpret this as a halt request or /* FALLTHROUGH */
* that the target stopped on it's own accord? case DBG_REASON_UNDEFINED:
*/
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
/* if we fail here, we won't talk to the target and it will
* be reported to be in the halted state */
break; break;
}
break;
case 12:
/* FIX!!!! here be dragons!!! We need to fail here so
* the target will interpreted as halted but we won't
* try to talk to it right now... a resume + halt seems
* to sync things up again. Please send an email to
* openocd development mailing list if you have hardware
* to donate to look into this problem....
*/
LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
target->debug_reason = DBG_REASON_DBGRQ;
break;
default:
LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason);
/* Oh agony! should we interpret this as a halt request or
* that the target stopped on it's own accord?
*/
target->debug_reason = DBG_REASON_DBGRQ;
/* if we fail here, we won't talk to the target and it will
* be reported to be in the halted state */
break;
} }
return ERROR_OK; return ERROR_OK;

18
src/target/arm9tdmi.c
View File

@@ -398,15 +398,15 @@ static void arm9tdmi_read_core_regs_target_buffer(struct target *target,
if (mask & (1 << i)) if (mask & (1 << i))
/* nothing fetched, STM in MEMORY (i'th cycle) */ /* nothing fetched, STM in MEMORY (i'th cycle) */
switch (size) { switch (size) {
case 4: case 4:
arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
break; break;
case 2: case 2:
arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
break; break;
case 1: case 1:
arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
break; break;
} }
} }
} }

38
src/target/arm_dap.c
View File

@@ -442,28 +442,28 @@ COMMAND_HANDLER(handle_dap_info_command)
} }
switch (CMD_ARGC) { switch (CMD_ARGC) {
case 0: case 0:
apsel = dap->apsel; apsel = dap->apsel;
break; break;
case 1: case 1:
if (!strcmp(CMD_ARGV[0], "root")) { if (!strcmp(CMD_ARGV[0], "root")) {
if (!is_adiv6(dap)) { if (!is_adiv6(dap)) {
command_print(CMD, "Option \"root\" not allowed with ADIv5 DAP"); command_print(CMD, "Option \"root\" not allowed with ADIv5 DAP");
return ERROR_COMMAND_ARGUMENT_INVALID; return ERROR_COMMAND_ARGUMENT_INVALID;
} }
int retval = adiv6_dap_read_baseptr(CMD, dap, &apsel); int retval = adiv6_dap_read_baseptr(CMD, dap, &apsel);
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
command_print(CMD, "Failed reading DAP baseptr"); command_print(CMD, "Failed reading DAP baseptr");
return retval; return retval;
}
break;
} }
COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
if (!is_ap_num_valid(dap, apsel))
return ERROR_COMMAND_SYNTAX_ERROR;
break; break;
default: }
COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel);
if (!is_ap_num_valid(dap, apsel))
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
} }
struct adiv5_ap *ap = dap_get_ap(dap, apsel); struct adiv5_ap *ap = dap_get_ap(dap, apsel);

1072
src/target/arm_disassembler.c
View File

File diff suppressed because it is too large Load Diff

348
src/target/arm_dpm.c
View File

@@ -171,24 +171,23 @@ static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int reg
uint32_t value_r0, value_r1; uint32_t value_r0, value_r1;
switch (regnum) { switch (regnum) {
case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
/* move from double word register to r0:r1: "vmov r0, r1, vm" /* move from double word register to r0:r1: "vmov r0, r1, vm"
* then read r0 via dcc * then read r0 via dcc
*/ */
retval = dpm->instr_read_data_r0(dpm, retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_VMOV(1, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4), ARMV4_5_VMOV(1, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
((regnum - ARM_VFP_V3_D0) & 0xf)), &value_r0); ((regnum - ARM_VFP_V3_D0) & 0xf)), &value_r0);
if (retval != ERROR_OK) if (retval != ERROR_OK)
break;
/* read r1 via dcc */
retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
&value_r1);
break; break;
default:
break; /* read r1 via dcc */
retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
&value_r1);
break;
default:
break;
} }
if (retval == ERROR_OK) { if (retval == ERROR_OK) {
@@ -210,54 +209,54 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
int retval; int retval;
switch (regnum) { switch (regnum) {
case 0 ... 14: case 0 ... 14:
/* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */ /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
retval = dpm->instr_read_data_dcc(dpm, retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, regnum, 0, 5, 0), ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
&value); &value);
break; break;
case 15:/* PC case 15:/* PC
* "MOV r0, pc"; then return via DCC */ * "MOV r0, pc"; then return via DCC */
retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value); retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
/* NOTE: this seems like a slightly awkward place to update /* NOTE: this seems like a slightly awkward place to update
* this value ... but if the PC gets written (the only way * this value ... but if the PC gets written (the only way
* to change what we compute), the arch spec says subsequent * to change what we compute), the arch spec says subsequent
* reads return values which are "unpredictable". So this * reads return values which are "unpredictable". So this
* is always right except in those broken-by-intent cases. * is always right except in those broken-by-intent cases.
*/ */
switch (dpm->arm->core_state) { switch (dpm->arm->core_state) {
case ARM_STATE_ARM: case ARM_STATE_ARM:
value -= 8; value -= 8;
break;
case ARM_STATE_THUMB:
case ARM_STATE_THUMB_EE:
value -= 4;
break;
case ARM_STATE_JAZELLE:
/* core-specific ... ? */
LOG_TARGET_WARNING(dpm->arm->target, "Jazelle PC adjustment unknown");
break;
default:
LOG_TARGET_WARNING(dpm->arm->target, "unknown core state");
break;
}
break; break;
case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: case ARM_STATE_THUMB:
return dpm_read_reg_u64(dpm, r, regnum); case ARM_STATE_THUMB_EE:
case ARM_VFP_V3_FPSCR: value -= 4;
/* "VMRS r0, FPSCR"; then return via DCC */ break;
retval = dpm->instr_read_data_r0(dpm, case ARM_STATE_JAZELLE:
ARMV4_5_VMRS(0), &value); /* core-specific ... ? */
LOG_TARGET_WARNING(dpm->arm->target, "Jazelle PC adjustment unknown");
break; break;
default: default:
/* 16: "MRS r0, CPSR"; then return via DCC LOG_TARGET_WARNING(dpm->arm->target, "unknown core state");
* 17: "MRS r0, SPSR"; then return via DCC
*/
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRS(0, regnum & 1),
&value);
break; break;
}
break;
case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
return dpm_read_reg_u64(dpm, r, regnum);
case ARM_VFP_V3_FPSCR:
/* "VMRS r0, FPSCR"; then return via DCC */
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_VMRS(0), &value);
break;
default:
/* 16: "MRS r0, CPSR"; then return via DCC
* 17: "MRS r0, SPSR"; then return via DCC
*/
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRS(0, regnum & 1),
&value);
break;
} }
if (retval == ERROR_OK) { if (retval == ERROR_OK) {
@@ -279,24 +278,23 @@ static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int re
uint32_t value_r1 = buf_get_u32(r->value + 4, 0, 32); uint32_t value_r1 = buf_get_u32(r->value + 4, 0, 32);
switch (regnum) { switch (regnum) {
case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
/* write value_r1 to r1 via dcc */ /* write value_r1 to r1 via dcc */
retval = dpm->instr_write_data_dcc(dpm, retval = dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, 1, 0, 5, 0), ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
value_r1); value_r1);
if (retval != ERROR_OK) if (retval != ERROR_OK)
break;
/* write value_r0 to r0 via dcc then,
* move to double word register from r0:r1: "vmov vm, r0, r1"
*/
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_VMOV(0, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
((regnum - ARM_VFP_V3_D0) & 0xf)), value_r0);
break; break;
default:
break; /* write value_r0 to r0 via dcc then,
* move to double word register from r0:r1: "vmov vm, r0, r1"
*/
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_VMOV(0, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
((regnum - ARM_VFP_V3_D0) & 0xf)), value_r0);
break;
default:
break;
} }
if (retval == ERROR_OK) { if (retval == ERROR_OK) {
@@ -315,37 +313,37 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum
uint32_t value = buf_get_u32(r->value, 0, 32); uint32_t value = buf_get_u32(r->value, 0, 32);
switch (regnum) { switch (regnum) {
case 0 ... 14: case 0 ... 14:
/* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */ /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
retval = dpm->instr_write_data_dcc(dpm, retval = dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, regnum, 0, 5, 0), ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
value); value);
break; break;
case 15:/* PC case 15:/* PC
* read r0 from DCC; then "MOV pc, r0" */ * read r0 from DCC; then "MOV pc, r0" */
retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value); retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
break; break;
case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
return dpm_write_reg_u64(dpm, r, regnum); return dpm_write_reg_u64(dpm, r, regnum);
case ARM_VFP_V3_FPSCR: case ARM_VFP_V3_FPSCR:
/* move to r0 from DCC, then "VMSR FPSCR, r0" */ /* move to r0 from DCC, then "VMSR FPSCR, r0" */
retval = dpm->instr_write_data_r0(dpm, retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_VMSR(0), value); ARMV4_5_VMSR(0), value);
break; break;
default: default:
/* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf" /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
* 17: read r0 from DCC, then "MSR r0, SPSR_cxsf" * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
*/ */
retval = dpm->instr_write_data_r0(dpm, retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MSR_GP(0, 0xf, regnum & 1), ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
value); value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
if (regnum == 16 && dpm->instr_cpsr_sync) if (regnum == 16 && dpm->instr_cpsr_sync)
retval = dpm->instr_cpsr_sync(dpm); retval = dpm->instr_cpsr_sync(dpm);
break; break;
} }
if (retval == ERROR_OK) { if (retval == ERROR_OK) {
@@ -655,24 +653,24 @@ static enum arm_mode dpm_mapmode(struct arm *arm,
return ARM_MODE_ANY; return ARM_MODE_ANY;
switch (num) { switch (num) {
/* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */ /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
case 0 ... 7: case 0 ... 7:
case 15: case 15:
case 16: case 16:
break; break;
/* r8..r12 aren't shadowed for anything except FIQ */ /* r8..r12 aren't shadowed for anything except FIQ */
case 8 ... 12: case 8 ... 12:
if (mode == ARM_MODE_FIQ) if (mode == ARM_MODE_FIQ)
return mode;
break;
/* r13/sp, and r14/lr are always shadowed */
case 13:
case 14:
case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR:
return mode; return mode;
default: break;
LOG_TARGET_WARNING(arm->target, "invalid register #%u", num); /* r13/sp, and r14/lr are always shadowed */
break; case 13:
case 14:
case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR:
return mode;
default:
LOG_TARGET_WARNING(arm->target, "invalid register #%u", num);
break;
} }
return ARM_MODE_ANY; return ARM_MODE_ANY;
} }
@@ -868,26 +866,26 @@ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
* v7 hardware, unaligned 4-byte ones too. * v7 hardware, unaligned 4-byte ones too.
*/ */
switch (length) { switch (length) {
case 1: case 1:
control |= (1 << (addr & 3)) << 5; control |= (1 << (addr & 3)) << 5;
break;
case 2:
/* require 2-byte alignment */
if (!(addr & 1)) {
control |= (3 << (addr & 2)) << 5;
break; break;
case 2: }
/* require 2-byte alignment */ /* FALL THROUGH */
if (!(addr & 1)) { case 4:
control |= (3 << (addr & 2)) << 5; /* require 4-byte alignment */
break; if (!(addr & 3)) {
} control |= 0xf << 5;
/* FALL THROUGH */ break;
case 4: }
/* require 4-byte alignment */ /* FALL THROUGH */
if (!(addr & 3)) { default:
control |= 0xf << 5; LOG_TARGET_ERROR(dpm->arm->target, "unsupported {break,watch}point length/alignment");
break; return ERROR_COMMAND_SYNTAX_ERROR;
}
/* FALL THROUGH */
default:
LOG_TARGET_ERROR(dpm->arm->target, "unsupported {break,watch}point length/alignment");
return ERROR_COMMAND_SYNTAX_ERROR;
} }
/* other shared control bits: /* other shared control bits:
@@ -974,15 +972,15 @@ static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t,
control = dwp->bpwp.control; control = dwp->bpwp.control;
switch (wp->rw) { switch (wp->rw) {
case WPT_READ: case WPT_READ:
control |= 1 << 3; control |= 1 << 3;
break; break;
case WPT_WRITE: case WPT_WRITE:
control |= 2 << 3; control |= 2 << 3;
break; break;
case WPT_ACCESS: case WPT_ACCESS:
control |= 3 << 3; control |= 3 << 3;
break; break;
} }
dwp->bpwp.control = control; dwp->bpwp.control = control;
@@ -1032,17 +1030,17 @@ static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr) void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
{ {
switch (dpm->arm->core_state) { switch (dpm->arm->core_state) {
case ARM_STATE_ARM: case ARM_STATE_ARM:
addr -= 8; addr -= 8;
break; break;
case ARM_STATE_THUMB: case ARM_STATE_THUMB:
case ARM_STATE_THUMB_EE: case ARM_STATE_THUMB_EE:
addr -= 4; addr -= 4;
break; break;
case ARM_STATE_JAZELLE: case ARM_STATE_JAZELLE:
case ARM_STATE_AARCH64: case ARM_STATE_AARCH64:
/* ?? */ /* ?? */
break; break;
} }
dpm->wp_addr = addr; dpm->wp_addr = addr;
} }
@@ -1061,21 +1059,21 @@ void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
/* Examine debug reason */ /* Examine debug reason */
switch (DSCR_ENTRY(dscr)) { switch (DSCR_ENTRY(dscr)) {
case DSCR_ENTRY_HALT_REQ: /* HALT request from debugger */ case DSCR_ENTRY_HALT_REQ: /* HALT request from debugger */
case DSCR_ENTRY_EXT_DBG_REQ: /* EDBGRQ */ case DSCR_ENTRY_EXT_DBG_REQ: /* EDBGRQ */
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
break; break;
case DSCR_ENTRY_BREAKPOINT: /* HW breakpoint */ case DSCR_ENTRY_BREAKPOINT: /* HW breakpoint */
case DSCR_ENTRY_BKPT_INSTR: /* vector catch */ case DSCR_ENTRY_BKPT_INSTR: /* vector catch */
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
break; break;
case DSCR_ENTRY_IMPRECISE_WATCHPT: /* asynch watchpoint */ case DSCR_ENTRY_IMPRECISE_WATCHPT: /* asynch watchpoint */
case DSCR_ENTRY_PRECISE_WATCHPT:/* precise watchpoint */ case DSCR_ENTRY_PRECISE_WATCHPT:/* precise watchpoint */
target->debug_reason = DBG_REASON_WATCHPOINT; target->debug_reason = DBG_REASON_WATCHPOINT;
break; break;
default: default:
target->debug_reason = DBG_REASON_UNDEFINED; target->debug_reason = DBG_REASON_UNDEFINED;
break; break;
} }
} }

205
src/target/arm_simulator.c
View File

@@ -130,86 +130,85 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim,
static int pass_condition(uint32_t cpsr, uint32_t opcode) static int pass_condition(uint32_t cpsr, uint32_t opcode)
{ {
switch ((opcode & 0xf0000000) >> 28) { switch ((opcode & 0xf0000000) >> 28) {
case 0x0: /* EQ */ case 0x0: /* EQ */
if (cpsr & 0x40000000) if (cpsr & 0x40000000)
return 1;
else
return 0;
case 0x1: /* NE */
if (!(cpsr & 0x40000000))
return 1;
else
return 0;
case 0x2: /* CS */
if (cpsr & 0x20000000)
return 1;
else
return 0;
case 0x3: /* CC */
if (!(cpsr & 0x20000000))
return 1;
else
return 0;
case 0x4: /* MI */
if (cpsr & 0x80000000)
return 1;
else
return 0;
case 0x5: /* PL */
if (!(cpsr & 0x80000000))
return 1;
else
return 0;
case 0x6: /* VS */
if (cpsr & 0x10000000)
return 1;
else
return 0;
case 0x7: /* VC */
if (!(cpsr & 0x10000000))
return 1;
else
return 0;
case 0x8: /* HI */
if ((cpsr & 0x20000000) && !(cpsr & 0x40000000))
return 1;
else
return 0;
case 0x9: /* LS */
if (!(cpsr & 0x20000000) || (cpsr & 0x40000000))
return 1;
else
return 0;
case 0xa: /* GE */
if (((cpsr & 0x80000000) && (cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && !(cpsr & 0x10000000)))
return 1;
else
return 0;
case 0xb: /* LT */
if (((cpsr & 0x80000000) && !(cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
return 1;
else
return 0;
case 0xc: /* GT */
if (!(cpsr & 0x40000000) &&
(((cpsr & 0x80000000) && (cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && !(cpsr & 0x10000000))))
return 1;
else
return 0;
case 0xd: /* LE */
if ((cpsr & 0x40000000) ||
((cpsr & 0x80000000) && !(cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
return 1;
else
return 0;
case 0xe:
case 0xf:
return 1; return 1;
else
return 0;
case 0x1: /* NE */
if (!(cpsr & 0x40000000))
return 1;
else
return 0;
case 0x2: /* CS */
if (cpsr & 0x20000000)
return 1;
else
return 0;
case 0x3: /* CC */
if (!(cpsr & 0x20000000))
return 1;
else
return 0;
case 0x4: /* MI */
if (cpsr & 0x80000000)
return 1;
else
return 0;
case 0x5: /* PL */
if (!(cpsr & 0x80000000))
return 1;
else
return 0;
case 0x6: /* VS */
if (cpsr & 0x10000000)
return 1;
else
return 0;
case 0x7: /* VC */
if (!(cpsr & 0x10000000))
return 1;
else
return 0;
case 0x8: /* HI */
if ((cpsr & 0x20000000) && !(cpsr & 0x40000000))
return 1;
else
return 0;
case 0x9: /* LS */
if (!(cpsr & 0x20000000) || (cpsr & 0x40000000))
return 1;
else
return 0;
case 0xa: /* GE */
if (((cpsr & 0x80000000) && (cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && !(cpsr & 0x10000000)))
return 1;
else
return 0;
case 0xb: /* LT */
if (((cpsr & 0x80000000) && !(cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
return 1;
else
return 0;
case 0xc: /* GT */
if (!(cpsr & 0x40000000) &&
(((cpsr & 0x80000000) && (cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && !(cpsr & 0x10000000))))
return 1;
else
return 0;
case 0xd: /* LE */
if ((cpsr & 0x40000000) ||
((cpsr & 0x80000000) && !(cpsr & 0x10000000))
|| (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
return 1;
else
return 0;
case 0xe:
case 0xf:
return 1;
} }
LOG_ERROR("BUG: should never get here"); LOG_ERROR("BUG: should never get here");
@@ -510,18 +509,18 @@ static int arm_simulate_step_core(struct target *target,
} }
switch (instruction.info.load_store_multiple.addressing_mode) { switch (instruction.info.load_store_multiple.addressing_mode) {
case 0: /* Increment after */ case 0: /* Increment after */
/* rn = rn; */ /* rn = rn; */
break; break;
case 1: /* Increment before */ case 1: /* Increment before */
rn = rn + 4; rn = rn + 4;
break; break;
case 2: /* Decrement after */ case 2: /* Decrement after */
rn = rn - (bits_set * 4) + 4; rn = rn - (bits_set * 4) + 4;
break; break;
case 3: /* Decrement before */ case 3: /* Decrement before */
rn = rn - (bits_set * 4); rn = rn - (bits_set * 4);
break; break;
} }
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
@@ -590,18 +589,18 @@ static int arm_simulate_step_core(struct target *target,
} }
switch (instruction.info.load_store_multiple.addressing_mode) { switch (instruction.info.load_store_multiple.addressing_mode) {
case 0: /* Increment after */ case 0: /* Increment after */
/* rn = rn; */ /* rn = rn; */
break; break;
case 1: /* Increment before */ case 1: /* Increment before */
rn = rn + 4; rn = rn + 4;
break; break;
case 2: /* Decrement after */ case 2: /* Decrement after */
rn = rn - (bits_set * 4) + 4; rn = rn - (bits_set * 4) + 4;
break; break;
case 3: /* Decrement before */ case 3: /* Decrement before */
rn = rn - (bits_set * 4); rn = rn - (bits_set * 4);
break; break;
} }
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {

182
src/target/armv4_5.c
View File

@@ -192,30 +192,30 @@ bool is_arm_mode(unsigned int psr_mode)
int arm_mode_to_number(enum arm_mode mode) int arm_mode_to_number(enum arm_mode mode)
{ {
switch (mode) { switch (mode) {
case ARM_MODE_ANY: case ARM_MODE_ANY:
/* map MODE_ANY to user mode */ /* map MODE_ANY to user mode */
case ARM_MODE_USR: case ARM_MODE_USR:
return 0; return 0;
case ARM_MODE_FIQ: case ARM_MODE_FIQ:
return 1; return 1;
case ARM_MODE_IRQ: case ARM_MODE_IRQ:
return 2; return 2;
case ARM_MODE_SVC: case ARM_MODE_SVC:
return 3; return 3;
case ARM_MODE_ABT: case ARM_MODE_ABT:
return 4; return 4;
case ARM_MODE_UND: case ARM_MODE_UND:
return 5; return 5;
case ARM_MODE_SYS: case ARM_MODE_SYS:
return 6; return 6;
case ARM_MODE_MON: case ARM_MODE_MON:
case ARM_MODE_1176_MON: case ARM_MODE_1176_MON:
return 7; return 7;
case ARM_MODE_HYP: case ARM_MODE_HYP:
return 8; return 8;
default: default:
LOG_ERROR("invalid mode value encountered %d", mode); LOG_ERROR("invalid mode value encountered %d", mode);
return -1; return -1;
} }
} }
@@ -223,27 +223,27 @@ int arm_mode_to_number(enum arm_mode mode)
enum arm_mode armv4_5_number_to_mode(int number) enum arm_mode armv4_5_number_to_mode(int number)
{ {
switch (number) { switch (number) {
case 0: case 0:
return ARM_MODE_USR; return ARM_MODE_USR;
case 1: case 1:
return ARM_MODE_FIQ; return ARM_MODE_FIQ;
case 2: case 2:
return ARM_MODE_IRQ; return ARM_MODE_IRQ;
case 3: case 3:
return ARM_MODE_SVC; return ARM_MODE_SVC;
case 4: case 4:
return ARM_MODE_ABT; return ARM_MODE_ABT;
case 5: case 5:
return ARM_MODE_UND; return ARM_MODE_UND;
case 6: case 6:
return ARM_MODE_SYS; return ARM_MODE_SYS;
case 7: case 7:
return ARM_MODE_MON; return ARM_MODE_MON;
case 8: case 8:
return ARM_MODE_HYP; return ARM_MODE_HYP;
default: default:
LOG_ERROR("mode index out of bounds %d", number); LOG_ERROR("mode index out of bounds %d", number);
return ARM_MODE_ANY; return ARM_MODE_ANY;
} }
} }
@@ -864,26 +864,26 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
/* label this bank of registers (or shadows) */ /* label this bank of registers (or shadows) */
switch (arm_mode_data[mode].psr) { switch (arm_mode_data[mode].psr) {
case ARM_MODE_SYS: case ARM_MODE_SYS:
continue;
case ARM_MODE_USR:
name = "System and User";
sep = "";
break;
case ARM_MODE_HYP:
if (arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue; continue;
case ARM_MODE_USR: /* FALLTHROUGH */
name = "System and User"; case ARM_MODE_MON:
sep = ""; case ARM_MODE_1176_MON:
break; if (arm->core_type != ARM_CORE_TYPE_SEC_EXT
case ARM_MODE_HYP: && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
if (arm->core_type != ARM_CORE_TYPE_VIRT_EXT) continue;
continue; /* FALLTHROUGH */
/* FALLTHROUGH */ default:
case ARM_MODE_MON: name = arm_mode_data[mode].name;
case ARM_MODE_1176_MON: shadow = "shadow ";
if (arm->core_type != ARM_CORE_TYPE_SEC_EXT break;
&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
/* FALLTHROUGH */
default:
name = arm_mode_data[mode].name;
shadow = "shadow ";
break;
} }
command_print(CMD, "%s%s mode %sregisters", command_print(CMD, "%s%s mode %sregisters",
sep, name, shadow); sep, name, shadow);
@@ -974,26 +974,26 @@ COMMAND_HANDLER(handle_arm_disassemble_command)
} }
switch (CMD_ARGC) { switch (CMD_ARGC) {
case 3: case 3:
if (strcmp(CMD_ARGV[2], "thumb") != 0) if (strcmp(CMD_ARGV[2], "thumb") != 0)
return ERROR_COMMAND_SYNTAX_ERROR;
thumb = true;
/* FALL THROUGH */
case 2:
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], count);
/* FALL THROUGH */
case 1:
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
if (address & 0x01) {
if (!thumb) {
command_print(CMD, "Disassemble as Thumb");
thumb = true;
}
address &= ~1;
}
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
thumb = true;
/* FALL THROUGH */
case 2:
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], count);
/* FALL THROUGH */
case 1:
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
if (address & 0x01) {
if (!thumb) {
command_print(CMD, "Disassemble as Thumb");
thumb = true;
}
address &= ~1;
}
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
} }
return arm_disassemble(CMD, target, address, count, thumb); return arm_disassemble(CMD, target, address, count, thumb);
@@ -1314,14 +1314,14 @@ int arm_get_gdb_reg_list(struct target *target,
case REG_CLASS_ALL: case REG_CLASS_ALL:
switch (arm->core_type) { switch (arm->core_type) {
case ARM_CORE_TYPE_SEC_EXT: case ARM_CORE_TYPE_SEC_EXT:
*reg_list_size = 51; *reg_list_size = 51;
break; break;
case ARM_CORE_TYPE_VIRT_EXT: case ARM_CORE_TYPE_VIRT_EXT:
*reg_list_size = 53; *reg_list_size = 53;
break; break;
default: default:
*reg_list_size = 48; *reg_list_size = 48;
} }
unsigned int list_size_core = *reg_list_size; unsigned int list_size_core = *reg_list_size;
if (arm->arm_vfp_version == ARM_VFP_V3) if (arm->arm_vfp_version == ARM_VFP_V3)

64
src/target/armv7a_mmu.c
View File

@@ -73,40 +73,40 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
NS == 1 ? "not" : "", NS == 1 ? "not" : "",
SS == 0 ? "not" : ""); SS == 0 ? "not" : "");
switch (OUTER) { switch (OUTER) {
case 0: case 0:
LOG_INFO("outer: Non-Cacheable"); LOG_INFO("outer: Non-Cacheable");
break; break;
case 1: case 1:
LOG_INFO("outer: Write-Back, Write-Allocate"); LOG_INFO("outer: Write-Back, Write-Allocate");
break; break;
case 2: case 2:
LOG_INFO("outer: Write-Through, No Write-Allocate"); LOG_INFO("outer: Write-Through, No Write-Allocate");
break; break;
case 3: case 3:
LOG_INFO("outer: Write-Back, no Write-Allocate"); LOG_INFO("outer: Write-Back, no Write-Allocate");
break; break;
} }
switch (INNER) { switch (INNER) {
case 0: case 0:
LOG_INFO("inner: Non-Cacheable"); LOG_INFO("inner: Non-Cacheable");
break; break;
case 1: case 1:
LOG_INFO("inner: Strongly-ordered"); LOG_INFO("inner: Strongly-ordered");
break; break;
case 3: case 3:
LOG_INFO("inner: Device"); LOG_INFO("inner: Device");
break; break;
case 5: case 5:
LOG_INFO("inner: Write-Back, Write-Allocate"); LOG_INFO("inner: Write-Back, Write-Allocate");
break; break;
case 6: case 6:
LOG_INFO("inner: Write-Through"); LOG_INFO("inner: Write-Through");
break; break;
case 7: case 7:
LOG_INFO("inner: Write-Back, no Write-Allocate"); LOG_INFO("inner: Write-Back, no Write-Allocate");
break; break;
default: default:
LOG_INFO("inner: %" PRIx32 " ???", INNER); LOG_INFO("inner: %" PRIx32 " ???", INNER);
} }
} }

90
src/target/armv8.c
View File

@@ -120,27 +120,27 @@ static uint8_t armv8_pa_size(uint32_t ps)
{ {
uint8_t ret = 0; uint8_t ret = 0;
switch (ps) { switch (ps) {
case 0: case 0:
ret = 32; ret = 32;
break; break;
case 1: case 1:
ret = 36; ret = 36;
break; break;
case 2: case 2:
ret = 40; ret = 40;
break; break;
case 3: case 3:
ret = 42; ret = 42;
break; break;
case 4: case 4:
ret = 44; ret = 44;
break; break;
case 5: case 5:
ret = 48; ret = 48;
break; break;
default: default:
LOG_INFO("Unknown physical address size"); LOG_INFO("Unknown physical address size");
break; break;
} }
return ret; return ret;
} }
@@ -1070,18 +1070,18 @@ static void armv8_decode_cacheability(int attr)
return; return;
} }
switch (attr & 0xC) { switch (attr & 0xC) {
case 0: case 0:
LOG_USER_N("Write-Through Transient"); LOG_USER_N("Write-Through Transient");
break; break;
case 0x4: case 0x4:
LOG_USER_N("Write-Back Transient"); LOG_USER_N("Write-Back Transient");
break; break;
case 0x8: case 0x8:
LOG_USER_N("Write-Through Non-transient"); LOG_USER_N("Write-Through Non-transient");
break; break;
case 0xC: case 0xC:
LOG_USER_N("Write-Back Non-transient"); LOG_USER_N("Write-Back Non-transient");
break; break;
} }
if (attr & 2) if (attr & 2)
LOG_USER_N(" Read-Allocate"); LOG_USER_N(" Read-Allocate");
@@ -1108,18 +1108,18 @@ static void armv8_decode_memory_attr(int attr)
"Non-transient"); "Non-transient");
} else if ((attr & 0xF0) == 0) { } else if ((attr & 0xF0) == 0) {
switch (attr & 0xC) { switch (attr & 0xC) {
case 0: case 0:
LOG_USER_N("Device-nGnRnE Memory"); LOG_USER_N("Device-nGnRnE Memory");
break; break;
case 0x4: case 0x4:
LOG_USER_N("Device-nGnRE Memory"); LOG_USER_N("Device-nGnRE Memory");
break; break;
case 0x8: case 0x8:
LOG_USER_N("Device-nGRE Memory"); LOG_USER_N("Device-nGRE Memory");
break; break;
case 0xC: case 0xC:
LOG_USER_N("Device-GRE Memory"); LOG_USER_N("Device-GRE Memory");
break; break;
} }
if (attr & 1) if (attr & 1)
LOG_USER(", XS=0"); LOG_USER(", XS=0");

146
src/target/armv8_dpm.c
View File

@@ -426,17 +426,17 @@ static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t,
int retval; int retval;
switch (index_t) { switch (index_t) {
case 0 ... 15: /* breakpoints */ case 0 ... 15: /* breakpoints */
vr += CPUV8_DBG_BVR_BASE; vr += CPUV8_DBG_BVR_BASE;
cr += CPUV8_DBG_BCR_BASE; cr += CPUV8_DBG_BCR_BASE;
break; break;
case 16 ... 31: /* watchpoints */ case 16 ... 31: /* watchpoints */
vr += CPUV8_DBG_WVR_BASE; vr += CPUV8_DBG_WVR_BASE;
cr += CPUV8_DBG_WCR_BASE; cr += CPUV8_DBG_WCR_BASE;
index_t -= 16; index_t -= 16;
break; break;
default: default:
return ERROR_FAIL; return ERROR_FAIL;
} }
vr += 16 * index_t; vr += 16 * index_t;
cr += 16 * index_t; cr += 16 * index_t;
@@ -456,15 +456,15 @@ static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
uint32_t cr; uint32_t cr;
switch (index_t) { switch (index_t) {
case 0 ... 15: case 0 ... 15:
cr = armv8->debug_base + CPUV8_DBG_BCR_BASE; cr = armv8->debug_base + CPUV8_DBG_BCR_BASE;
break; break;
case 16 ... 31: case 16 ... 31:
cr = armv8->debug_base + CPUV8_DBG_WCR_BASE; cr = armv8->debug_base + CPUV8_DBG_WCR_BASE;
index_t -= 16; index_t -= 16;
break; break;
default: default:
return ERROR_FAIL; return ERROR_FAIL;
} }
cr += 16 * index_t; cr += 16 * index_t;
@@ -1127,26 +1127,26 @@ static int dpmv8_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
* v7 hardware, unaligned 4-byte ones too. * v7 hardware, unaligned 4-byte ones too.
*/ */
switch (length) { switch (length) {
case 1: case 1:
control |= (1 << (addr & 3)) << 5; control |= (1 << (addr & 3)) << 5;
break;
case 2:
/* require 2-byte alignment */
if (!(addr & 1)) {
control |= (3 << (addr & 2)) << 5;
break; break;
case 2: }
/* require 2-byte alignment */ /* FALL THROUGH */
if (!(addr & 1)) { case 4:
control |= (3 << (addr & 2)) << 5; /* require 4-byte alignment */
break; if (!(addr & 3)) {
} control |= 0xf << 5;
/* FALL THROUGH */ break;
case 4: }
/* require 4-byte alignment */ /* FALL THROUGH */
if (!(addr & 3)) { default:
control |= 0xf << 5; LOG_ERROR("unsupported {break,watch}point length/alignment");
break; return ERROR_COMMAND_SYNTAX_ERROR;
}
/* FALL THROUGH */
default:
LOG_ERROR("unsupported {break,watch}point length/alignment");
return ERROR_COMMAND_SYNTAX_ERROR;
} }
/* other shared control bits: /* other shared control bits:
@@ -1233,15 +1233,15 @@ static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t,
control = dwp->bpwp.control; control = dwp->bpwp.control;
switch (wp->rw) { switch (wp->rw) {
case WPT_READ: case WPT_READ:
control |= 1 << 3; control |= 1 << 3;
break; break;
case WPT_WRITE: case WPT_WRITE:
control |= 2 << 3; control |= 2 << 3;
break; break;
case WPT_ACCESS: case WPT_ACCESS:
control |= 3 << 3; control |= 3 << 3;
break; break;
} }
dwp->bpwp.control = control; dwp->bpwp.control = control;
@@ -1363,31 +1363,31 @@ void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
/* Examine debug reason */ /* Examine debug reason */
switch (DSCR_ENTRY(dscr)) { switch (DSCR_ENTRY(dscr)) {
/* FALL THROUGH -- assume a v6 core in abort mode */ /* FALL THROUGH -- assume a v6 core in abort mode */
case DSCRV8_ENTRY_EXT_DEBUG: /* EDBGRQ */ case DSCRV8_ENTRY_EXT_DEBUG: /* EDBGRQ */
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
break; break;
case DSCRV8_ENTRY_HALT_STEP_EXECLU: /* HALT step */ case DSCRV8_ENTRY_HALT_STEP_EXECLU: /* HALT step */
case DSCRV8_ENTRY_HALT_STEP_NORMAL: /* Halt step*/ case DSCRV8_ENTRY_HALT_STEP_NORMAL: /* Halt step*/
case DSCRV8_ENTRY_HALT_STEP: case DSCRV8_ENTRY_HALT_STEP:
target->debug_reason = DBG_REASON_SINGLESTEP; target->debug_reason = DBG_REASON_SINGLESTEP;
break; break;
case DSCRV8_ENTRY_HLT: /* HLT instruction (software breakpoint) */ case DSCRV8_ENTRY_HLT: /* HLT instruction (software breakpoint) */
case DSCRV8_ENTRY_BKPT: /* SW BKPT (?) */ case DSCRV8_ENTRY_BKPT: /* SW BKPT (?) */
case DSCRV8_ENTRY_RESET_CATCH: /* Reset catch */ case DSCRV8_ENTRY_RESET_CATCH: /* Reset catch */
case DSCRV8_ENTRY_OS_UNLOCK: /*OS unlock catch*/ case DSCRV8_ENTRY_OS_UNLOCK: /*OS unlock catch*/
case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/ case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
break; break;
case DSCRV8_ENTRY_WATCHPOINT: /* asynch watchpoint */ case DSCRV8_ENTRY_WATCHPOINT: /* asynch watchpoint */
target->debug_reason = DBG_REASON_WATCHPOINT; target->debug_reason = DBG_REASON_WATCHPOINT;
break; break;
case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/ case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/
target->debug_reason = DBG_REASON_EXC_CATCH; target->debug_reason = DBG_REASON_EXC_CATCH;
break; break;
default: default:
target->debug_reason = DBG_REASON_UNDEFINED; target->debug_reason = DBG_REASON_UNDEFINED;
break; break;
} }
} }

48
src/target/avr32_ap7k.c
View File

@@ -443,18 +443,18 @@ static int avr32_ap7k_read_memory(struct target *target, target_addr_t address,
return ERROR_TARGET_UNALIGNED_ACCESS; return ERROR_TARGET_UNALIGNED_ACCESS;
switch (size) { switch (size) {
case 4: case 4:
return avr32_jtag_read_memory32(&ap7k->jtag, address, count, return avr32_jtag_read_memory32(&ap7k->jtag, address, count,
(uint32_t *)(void *)buffer); (uint32_t *)(void *)buffer);
break; break;
case 2: case 2:
return avr32_jtag_read_memory16(&ap7k->jtag, address, count, return avr32_jtag_read_memory16(&ap7k->jtag, address, count,
(uint16_t *)(void *)buffer); (uint16_t *)(void *)buffer);
break; break;
case 1: case 1:
return avr32_jtag_read_memory8(&ap7k->jtag, address, count, buffer); return avr32_jtag_read_memory8(&ap7k->jtag, address, count, buffer);
default: default:
break; break;
} }
return ERROR_OK; return ERROR_OK;
@@ -483,18 +483,18 @@ static int avr32_ap7k_write_memory(struct target *target, target_addr_t address,
return ERROR_TARGET_UNALIGNED_ACCESS; return ERROR_TARGET_UNALIGNED_ACCESS;
switch (size) { switch (size) {
case 4: case 4:
return avr32_jtag_write_memory32(&ap7k->jtag, address, count, return avr32_jtag_write_memory32(&ap7k->jtag, address, count,
(uint32_t *)(void *)buffer); (uint32_t *)(void *)buffer);
break; break;
case 2: case 2:
return avr32_jtag_write_memory16(&ap7k->jtag, address, count, return avr32_jtag_write_memory16(&ap7k->jtag, address, count,
(uint16_t *)(void *)buffer); (uint16_t *)(void *)buffer);
break; break;
case 1: case 1:
return avr32_jtag_write_memory8(&ap7k->jtag, address, count, buffer); return avr32_jtag_write_memory8(&ap7k->jtag, address, count, buffer);
default: default:
break; break;
} }
return ERROR_OK; return ERROR_OK;

62
src/target/breakpoints.c
View File

@@ -72,22 +72,22 @@ static int breakpoint_add_internal(struct target *target,
retval = target_add_breakpoint(target, *breakpoint_p); retval = target_add_breakpoint(target, *breakpoint_p);
switch (retval) { switch (retval) {
case ERROR_OK: case ERROR_OK:
break; break;
case ERROR_TARGET_RESOURCE_NOT_AVAILABLE: case ERROR_TARGET_RESOURCE_NOT_AVAILABLE:
reason = "resource not available"; reason = "resource not available";
goto fail; goto fail;
case ERROR_TARGET_NOT_HALTED: case ERROR_TARGET_NOT_HALTED:
reason = "target running"; reason = "target running";
goto fail; goto fail;
default: default:
reason = "unknown reason"; reason = "unknown reason";
fail: fail:
LOG_TARGET_ERROR(target, "can't add breakpoint: %s", reason); LOG_TARGET_ERROR(target, "can't add breakpoint: %s", reason);
free((*breakpoint_p)->orig_instr); free((*breakpoint_p)->orig_instr);
free(*breakpoint_p); free(*breakpoint_p);
*breakpoint_p = NULL; *breakpoint_p = NULL;
return retval; return retval;
} }
LOG_TARGET_DEBUG(target, "added %s breakpoint at " TARGET_ADDR_FMT LOG_TARGET_DEBUG(target, "added %s breakpoint at " TARGET_ADDR_FMT
@@ -536,23 +536,23 @@ static int watchpoint_add_internal(struct target *target, target_addr_t address,
retval = target_add_watchpoint(target, *watchpoint_p); retval = target_add_watchpoint(target, *watchpoint_p);
switch (retval) { switch (retval) {
case ERROR_OK: case ERROR_OK:
break; break;
case ERROR_TARGET_RESOURCE_NOT_AVAILABLE: case ERROR_TARGET_RESOURCE_NOT_AVAILABLE:
reason = "resource not available"; reason = "resource not available";
goto bye; goto bye;
case ERROR_TARGET_NOT_HALTED: case ERROR_TARGET_NOT_HALTED:
reason = "target running"; reason = "target running";
goto bye; goto bye;
default: default:
reason = "unrecognized error"; reason = "unrecognized error";
bye: bye:
LOG_TARGET_ERROR(target, "can't add %s watchpoint at " TARGET_ADDR_FMT ", %s", LOG_TARGET_ERROR(target, "can't add %s watchpoint at " TARGET_ADDR_FMT ", %s",
watchpoint_rw_strings[(*watchpoint_p)->rw], watchpoint_rw_strings[(*watchpoint_p)->rw],
address, reason); address, reason);
free(*watchpoint_p); free(*watchpoint_p);
*watchpoint_p = NULL; *watchpoint_p = NULL;
return retval; return retval;
} }
LOG_TARGET_DEBUG(target, "added %s watchpoint at " TARGET_ADDR_FMT LOG_TARGET_DEBUG(target, "added %s watchpoint at " TARGET_ADDR_FMT

128
src/target/cortex_a.c
View File

@@ -580,17 +580,17 @@ static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t,
int retval; int retval;
switch (index_t) { switch (index_t) {
case 0 ... 15: /* breakpoints */ case 0 ... 15: /* breakpoints */
vr += CPUDBG_BVR_BASE; vr += CPUDBG_BVR_BASE;
cr += CPUDBG_BCR_BASE; cr += CPUDBG_BCR_BASE;
break; break;
case 16 ... 31: /* watchpoints */ case 16 ... 31: /* watchpoints */
vr += CPUDBG_WVR_BASE; vr += CPUDBG_WVR_BASE;
cr += CPUDBG_WCR_BASE; cr += CPUDBG_WCR_BASE;
index_t -= 16; index_t -= 16;
break; break;
default: default:
return ERROR_FAIL; return ERROR_FAIL;
} }
vr += 4 * index_t; vr += 4 * index_t;
cr += 4 * index_t; cr += 4 * index_t;
@@ -612,15 +612,15 @@ static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
uint32_t cr; uint32_t cr;
switch (index_t) { switch (index_t) {
case 0 ... 15: case 0 ... 15:
cr = a->armv7a_common.debug_base + CPUDBG_BCR_BASE; cr = a->armv7a_common.debug_base + CPUDBG_BCR_BASE;
break; break;
case 16 ... 31: case 16 ... 31:
cr = a->armv7a_common.debug_base + CPUDBG_WCR_BASE; cr = a->armv7a_common.debug_base + CPUDBG_WCR_BASE;
index_t -= 16; index_t -= 16;
break; break;
default: default:
return ERROR_FAIL; return ERROR_FAIL;
} }
cr += 4 * index_t; cr += 4 * index_t;
@@ -860,22 +860,22 @@ static int cortex_a_internal_restore(struct target *target, bool current,
* kill the return address * kill the return address
*/ */
switch (arm->core_state) { switch (arm->core_state) {
case ARM_STATE_ARM: case ARM_STATE_ARM:
resume_pc &= 0xFFFFFFFC; resume_pc &= 0xFFFFFFFC;
break; break;
case ARM_STATE_THUMB: case ARM_STATE_THUMB:
case ARM_STATE_THUMB_EE: case ARM_STATE_THUMB_EE:
/* When the return address is loaded into PC /* When the return address is loaded into PC
* bit 0 must be 1 to stay in Thumb state * bit 0 must be 1 to stay in Thumb state
*/ */
resume_pc |= 0x1; resume_pc |= 0x1;
break; break;
case ARM_STATE_JAZELLE: case ARM_STATE_JAZELLE:
LOG_ERROR("How do I resume into Jazelle state??"); LOG_ERROR("How do I resume into Jazelle state??");
return ERROR_FAIL; return ERROR_FAIL;
case ARM_STATE_AARCH64: case ARM_STATE_AARCH64:
LOG_ERROR("Shouldn't be in AARCH64 state"); LOG_ERROR("Shouldn't be in AARCH64 state");
return ERROR_FAIL; return ERROR_FAIL;
} }
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc); LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
buf_set_u32(arm->pc->value, 0, 32, resume_pc); buf_set_u32(arm->pc->value, 0, 32, resume_pc);
@@ -2350,20 +2350,20 @@ static int cortex_a_write_cpu_memory(struct target *target,
} else { } else {
/* Use slow path. Adjust size for aligned accesses */ /* Use slow path. Adjust size for aligned accesses */
switch (address % 4) { switch (address % 4) {
case 1: case 1:
case 3: case 3:
count *= size; count *= size;
size = 1; size = 1;
break; break;
case 2: case 2:
if (size == 4) { if (size == 4) {
count *= 2; count *= 2;
size = 2; size = 2;
} }
break; break;
case 0: case 0:
default: default:
break; break;
} }
retval = cortex_a_write_cpu_memory_slow(target, size, count, buffer, &dscr); retval = cortex_a_write_cpu_memory_slow(target, size, count, buffer, &dscr);
} }
@@ -2668,20 +2668,20 @@ static int cortex_a_read_cpu_memory(struct target *target,
} else { } else {
/* Use slow path. Adjust size for aligned accesses */ /* Use slow path. Adjust size for aligned accesses */
switch (address % 4) { switch (address % 4) {
case 1: case 1:
case 3: case 3:
count *= size; count *= size;
size = 1; size = 1;
break; break;
case 2: case 2:
if (size == 4) { if (size == 4) {
count *= 2; count *= 2;
size = 2; size = 2;
} }
break; break;
case 0: case 0:
default: default:
break; break;
} }
retval = cortex_a_read_cpu_memory_slow(target, size, count, buffer, &dscr); retval = cortex_a_read_cpu_memory_slow(target, size, count, buffer, &dscr);
} }

198
src/target/cortex_m.c
View File

@@ -472,22 +472,22 @@ static int cortex_m_set_maskints_for_halt(struct target *target)
{ {
struct cortex_m_common *cortex_m = target_to_cm(target); struct cortex_m_common *cortex_m = target_to_cm(target);
switch (cortex_m->isrmasking_mode) { switch (cortex_m->isrmasking_mode) {
case CORTEX_M_ISRMASK_AUTO: case CORTEX_M_ISRMASK_AUTO:
/* interrupts taken at resume, whether for step or run -> no mask */ /* interrupts taken at resume, whether for step or run -> no mask */
return cortex_m_set_maskints(target, false); return cortex_m_set_maskints(target, false);
case CORTEX_M_ISRMASK_OFF: case CORTEX_M_ISRMASK_OFF:
/* interrupts never masked */ /* interrupts never masked */
return cortex_m_set_maskints(target, false); return cortex_m_set_maskints(target, false);
case CORTEX_M_ISRMASK_ON: case CORTEX_M_ISRMASK_ON:
/* interrupts always masked */ /* interrupts always masked */
return cortex_m_set_maskints(target, true); return cortex_m_set_maskints(target, true);
case CORTEX_M_ISRMASK_STEPONLY: case CORTEX_M_ISRMASK_STEPONLY:
/* interrupts masked for single step only -> mask now if MASKINTS /* interrupts masked for single step only -> mask now if MASKINTS
* erratum, otherwise only mask before stepping */ * erratum, otherwise only mask before stepping */
return cortex_m_set_maskints(target, cortex_m->maskints_erratum); return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
} }
return ERROR_OK; return ERROR_OK;
} }
@@ -495,21 +495,21 @@ static int cortex_m_set_maskints_for_halt(struct target *target)
static int cortex_m_set_maskints_for_run(struct target *target) static int cortex_m_set_maskints_for_run(struct target *target)
{ {
switch (target_to_cm(target)->isrmasking_mode) { switch (target_to_cm(target)->isrmasking_mode) {
case CORTEX_M_ISRMASK_AUTO: case CORTEX_M_ISRMASK_AUTO:
/* interrupts taken at resume, whether for step or run -> no mask */ /* interrupts taken at resume, whether for step or run -> no mask */
return cortex_m_set_maskints(target, false); return cortex_m_set_maskints(target, false);
case CORTEX_M_ISRMASK_OFF: case CORTEX_M_ISRMASK_OFF:
/* interrupts never masked */ /* interrupts never masked */
return cortex_m_set_maskints(target, false); return cortex_m_set_maskints(target, false);
case CORTEX_M_ISRMASK_ON: case CORTEX_M_ISRMASK_ON:
/* interrupts always masked */ /* interrupts always masked */
return cortex_m_set_maskints(target, true); return cortex_m_set_maskints(target, true);
case CORTEX_M_ISRMASK_STEPONLY: case CORTEX_M_ISRMASK_STEPONLY:
/* interrupts masked for single step only -> no mask */ /* interrupts masked for single step only -> no mask */
return cortex_m_set_maskints(target, false); return cortex_m_set_maskints(target, false);
} }
return ERROR_OK; return ERROR_OK;
} }
@@ -517,21 +517,21 @@ static int cortex_m_set_maskints_for_run(struct target *target)
static int cortex_m_set_maskints_for_step(struct target *target) static int cortex_m_set_maskints_for_step(struct target *target)
{ {
switch (target_to_cm(target)->isrmasking_mode) { switch (target_to_cm(target)->isrmasking_mode) {
case CORTEX_M_ISRMASK_AUTO: case CORTEX_M_ISRMASK_AUTO:
/* the auto-interrupt should already be done -> mask */ /* the auto-interrupt should already be done -> mask */
return cortex_m_set_maskints(target, true); return cortex_m_set_maskints(target, true);
case CORTEX_M_ISRMASK_OFF: case CORTEX_M_ISRMASK_OFF:
/* interrupts never masked */ /* interrupts never masked */
return cortex_m_set_maskints(target, false); return cortex_m_set_maskints(target, false);
case CORTEX_M_ISRMASK_ON: case CORTEX_M_ISRMASK_ON:
/* interrupts always masked */ /* interrupts always masked */
return cortex_m_set_maskints(target, true); return cortex_m_set_maskints(target, true);
case CORTEX_M_ISRMASK_STEPONLY: case CORTEX_M_ISRMASK_STEPONLY:
/* interrupts masked for single step only -> mask */ /* interrupts masked for single step only -> mask */
return cortex_m_set_maskints(target, true); return cortex_m_set_maskints(target, true);
} }
return ERROR_OK; return ERROR_OK;
} }
@@ -739,61 +739,61 @@ static int cortex_m_examine_exception_reason(struct target *target)
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
switch (armv7m->exception_number) { switch (armv7m->exception_number) {
case 2: /* NMI */ case 2: /* NMI */
break; break;
case 3: /* Hard Fault */ case 3: /* Hard Fault */
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr); retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
if (except_sr & 0x40000000) {
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
if (except_sr & 0x40000000) { }
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr); break;
if (retval != ERROR_OK) case 4: /* Memory Management */
return retval; retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
} if (retval != ERROR_OK)
break; return retval;
case 4: /* Memory Management */ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); if (retval != ERROR_OK)
if (retval != ERROR_OK) return retval;
return retval; break;
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar); case 5: /* Bus Fault */
if (retval != ERROR_OK) retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
return retval; if (retval != ERROR_OK)
break; return retval;
case 5: /* Bus Fault */ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); if (retval != ERROR_OK)
if (retval != ERROR_OK) return retval;
return retval; break;
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar); case 6: /* Usage Fault */
if (retval != ERROR_OK) retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
return retval; if (retval != ERROR_OK)
break; return retval;
case 6: /* Usage Fault */ break;
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); case 7: /* Secure Fault */
if (retval != ERROR_OK) retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
return retval; if (retval != ERROR_OK)
break; return retval;
case 7: /* Secure Fault */ retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr); if (retval != ERROR_OK)
if (retval != ERROR_OK) return retval;
return retval; break;
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar); case 11: /* SVCall */
if (retval != ERROR_OK) break;
return retval; case 12: /* Debug Monitor */
break; retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
case 11: /* SVCall */ if (retval != ERROR_OK)
break; return retval;
case 12: /* Debug Monitor */ break;
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr); case 14: /* PendSV */
if (retval != ERROR_OK) break;
return retval; case 15: /* SysTick */
break; break;
case 14: /* PendSV */ default:
break; except_sr = 0;
case 15: /* SysTick */ break;
break;
default:
except_sr = 0;
break;
} }
retval = dap_run(swjdp); retval = dap_run(swjdp);
if (retval == ERROR_OK) if (retval == ERROR_OK)
@@ -3217,17 +3217,17 @@ COMMAND_HANDLER(handle_cortex_m_reset_config_command)
} }
switch (cortex_m->soft_reset_config) { switch (cortex_m->soft_reset_config) {
case CORTEX_M_RESET_SYSRESETREQ: case CORTEX_M_RESET_SYSRESETREQ:
reset_config = "sysresetreq"; reset_config = "sysresetreq";
break; break;
case CORTEX_M_RESET_VECTRESET: case CORTEX_M_RESET_VECTRESET:
reset_config = "vectreset"; reset_config = "vectreset";
break; break;
default: default:
reset_config = "unknown"; reset_config = "unknown";
break; break;
} }
command_print(CMD, "cortex_m reset_config %s", reset_config); command_print(CMD, "cortex_m reset_config %s", reset_config);

371
src/target/dsp563xx.c
View File

@@ -741,37 +741,37 @@ static int dsp563xx_read_register(struct target *target, int num, int force)
arch_info = dsp563xx->core_cache->reg_list[num].arch_info; arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
switch (arch_info->num) { switch (arch_info->num) {
case DSP563XX_REG_IDX_SSH: case DSP563XX_REG_IDX_SSH:
err = dsp563xx_reg_ssh_read(target); err = dsp563xx_reg_ssh_read(target);
break; break;
case DSP563XX_REG_IDX_SSL: case DSP563XX_REG_IDX_SSL:
err = dsp563xx_reg_ssl_read(target); err = dsp563xx_reg_ssl_read(target);
break; break;
case DSP563XX_REG_IDX_PC: case DSP563XX_REG_IDX_PC:
err = dsp563xx_reg_pc_read(target); err = dsp563xx_reg_pc_read(target);
break; break;
case DSP563XX_REG_IDX_IPRC: case DSP563XX_REG_IDX_IPRC:
case DSP563XX_REG_IDX_IPRP: case DSP563XX_REG_IDX_IPRP:
case DSP563XX_REG_IDX_BCR: case DSP563XX_REG_IDX_BCR:
case DSP563XX_REG_IDX_DCR: case DSP563XX_REG_IDX_DCR:
case DSP563XX_REG_IDX_AAR0: case DSP563XX_REG_IDX_AAR0:
case DSP563XX_REG_IDX_AAR1: case DSP563XX_REG_IDX_AAR1:
case DSP563XX_REG_IDX_AAR2: case DSP563XX_REG_IDX_AAR2:
case DSP563XX_REG_IDX_AAR3: case DSP563XX_REG_IDX_AAR3:
err = dsp563xx_reg_read_high_io(target, err = dsp563xx_reg_read_high_io(target,
arch_info->instr_mask, &data); arch_info->instr_mask, &data);
if (err == ERROR_OK) { if (err == ERROR_OK) {
dsp563xx->core_regs[num] = data; dsp563xx->core_regs[num] = data;
dsp563xx->read_core_reg(target, num); dsp563xx->read_core_reg(target, num);
} }
break; break;
default: default:
err = dsp563xx_reg_read(target, arch_info->eame, &data); err = dsp563xx_reg_read(target, arch_info->eame, &data);
if (err == ERROR_OK) { if (err == ERROR_OK) {
dsp563xx->core_regs[num] = data; dsp563xx->core_regs[num] = data;
dsp563xx->read_core_reg(target, num); dsp563xx->read_core_reg(target, num);
} }
break; break;
} }
} }
@@ -793,35 +793,34 @@ static int dsp563xx_write_register(struct target *target, int num, int force)
dsp563xx->write_core_reg(target, num); dsp563xx->write_core_reg(target, num);
switch (arch_info->num) { switch (arch_info->num) {
case DSP563XX_REG_IDX_SSH: case DSP563XX_REG_IDX_SSH:
err = dsp563xx_reg_ssh_write(target); err = dsp563xx_reg_ssh_write(target);
break; break;
case DSP563XX_REG_IDX_PC: case DSP563XX_REG_IDX_PC:
/* pc is updated on resume, no need to write it here */ /* pc is updated on resume, no need to write it here */
break; break;
case DSP563XX_REG_IDX_IPRC: case DSP563XX_REG_IDX_IPRC:
case DSP563XX_REG_IDX_IPRP: case DSP563XX_REG_IDX_IPRP:
case DSP563XX_REG_IDX_BCR: case DSP563XX_REG_IDX_BCR:
case DSP563XX_REG_IDX_DCR: case DSP563XX_REG_IDX_DCR:
case DSP563XX_REG_IDX_AAR0: case DSP563XX_REG_IDX_AAR0:
case DSP563XX_REG_IDX_AAR1: case DSP563XX_REG_IDX_AAR1:
case DSP563XX_REG_IDX_AAR2: case DSP563XX_REG_IDX_AAR2:
case DSP563XX_REG_IDX_AAR3: case DSP563XX_REG_IDX_AAR3:
err = dsp563xx_reg_write_high_io(target, err = dsp563xx_reg_write_high_io(target,
arch_info->instr_mask, arch_info->instr_mask,
dsp563xx->core_regs[num]); dsp563xx->core_regs[num]);
break; break;
default: default:
err = dsp563xx_reg_write(target, err = dsp563xx_reg_write(target,
arch_info->instr_mask, arch_info->instr_mask,
dsp563xx->core_regs[num]); dsp563xx->core_regs[num]);
if (err == ERROR_OK && arch_info->num == DSP563XX_REG_IDX_SP) { if (err == ERROR_OK && arch_info->num == DSP563XX_REG_IDX_SP) {
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].valid = 0; dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].valid = 0;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].valid = 0; dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].valid = 0;
} }
break;
break;
} }
} }
@@ -1488,14 +1487,14 @@ static int dsp563xx_get_default_memory(void)
return MEM_P; return MEM_P;
switch (c[0]) { switch (c[0]) {
case '1': case '1':
return MEM_X; return MEM_X;
case '2': case '2':
return MEM_Y; return MEM_Y;
case '3': case '3':
return MEM_L; return MEM_L;
default: default:
break; break;
} }
return MEM_P; return MEM_P;
@@ -1527,18 +1526,18 @@ static int dsp563xx_read_memory_core(struct target *target,
} }
switch (mem_type) { switch (mem_type) {
case MEM_X: case MEM_X:
/* TODO: mark effected queued registers */ /* TODO: mark effected queued registers */
move_cmd = 0x61d800; move_cmd = 0x61d800;
break; break;
case MEM_Y: case MEM_Y:
move_cmd = 0x69d800; move_cmd = 0x69d800;
break; break;
case MEM_P: case MEM_P:
move_cmd = 0x07d891; move_cmd = 0x07d891;
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
/* we use r0 to store temporary data */ /* we use r0 to store temporary data */
@@ -1708,19 +1707,19 @@ static int dsp563xx_write_memory_core(struct target *target,
} }
switch (mem_type) { switch (mem_type) {
case MEM_X: case MEM_X:
/* invalidate affected x registers */ /* invalidate affected x registers */
dsp563xx_invalidate_x_context(target, address, address + count - 1); dsp563xx_invalidate_x_context(target, address, address + count - 1);
move_cmd = 0x615800; move_cmd = 0x615800;
break; break;
case MEM_Y: case MEM_Y:
move_cmd = 0x695800; move_cmd = 0x695800;
break; break;
case MEM_P: case MEM_P:
move_cmd = 0x075891; move_cmd = 0x075891;
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
/* we use r0 to store temporary data */ /* we use r0 to store temporary data */
@@ -1894,55 +1893,55 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres
if (err == ERROR_OK) { if (err == ERROR_OK) {
obcr_value |= OBCR_B0_OR_B1; obcr_value |= OBCR_B0_OR_B1;
switch (mem_type) { switch (mem_type) {
case MEM_X: case MEM_X:
obcr_value |= OBCR_BP_MEM_X; obcr_value |= OBCR_BP_MEM_X;
break; break;
case MEM_Y: case MEM_Y:
obcr_value |= OBCR_BP_MEM_Y; obcr_value |= OBCR_BP_MEM_Y;
break; break;
case MEM_P: case MEM_P:
obcr_value |= OBCR_BP_MEM_P; obcr_value |= OBCR_BP_MEM_P;
break; break;
default: default:
LOG_ERROR("Unknown mem_type parameter (%" PRIu32 ")", mem_type); LOG_ERROR("Unknown mem_type parameter (%" PRIu32 ")", mem_type);
err = ERROR_TARGET_INVALID; err = ERROR_TARGET_INVALID;
} }
} }
if (err == ERROR_OK) { if (err == ERROR_OK) {
switch (rw) { switch (rw) {
case WPT_READ: case WPT_READ:
obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ); obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ);
break; break;
case WPT_WRITE: case WPT_WRITE:
obcr_value |= OBCR_BP_0(OBCR_BP_ON_WRITE); obcr_value |= OBCR_BP_0(OBCR_BP_ON_WRITE);
break; break;
case WPT_ACCESS: case WPT_ACCESS:
obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ|OBCR_BP_ON_WRITE); obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ | OBCR_BP_ON_WRITE);
break; break;
default: default:
LOG_ERROR("Unsupported write mode (%d)", rw); LOG_ERROR("Unsupported write mode (%d)", rw);
err = ERROR_TARGET_INVALID; err = ERROR_TARGET_INVALID;
} }
} }
if (err == ERROR_OK) { if (err == ERROR_OK) {
switch (cond) { switch (cond) {
case EQUAL: case EQUAL:
obcr_value |= OBCR_BP_0(OBCR_BP_CC_EQUAL); obcr_value |= OBCR_BP_0(OBCR_BP_CC_EQUAL);
break; break;
case NOT_EQUAL: case NOT_EQUAL:
obcr_value |= OBCR_BP_0(OBCR_BP_CC_NOT_EQUAL); obcr_value |= OBCR_BP_0(OBCR_BP_CC_NOT_EQUAL);
break; break;
case LESS_THAN: case LESS_THAN:
obcr_value |= OBCR_BP_0(OBCR_BP_CC_LESS_THAN); obcr_value |= OBCR_BP_0(OBCR_BP_CC_LESS_THAN);
break; break;
case GREATER: case GREATER:
obcr_value |= OBCR_BP_0(OBCR_BP_CC_GREATER_THAN); obcr_value |= OBCR_BP_0(OBCR_BP_CC_GREATER_THAN);
break; break;
default: default:
LOG_ERROR("Unsupported condition code (%d)", cond); LOG_ERROR("Unsupported condition code (%d)", cond);
err = ERROR_TARGET_INVALID; err = ERROR_TARGET_INVALID;
} }
} }
@@ -2004,17 +2003,17 @@ COMMAND_HANDLER(dsp563xx_add_watchpoint_command)
uint32_t mem_type = 0; uint32_t mem_type = 0;
switch (CMD_NAME[2]) { switch (CMD_NAME[2]) {
case 'x': case 'x':
mem_type = MEM_X; mem_type = MEM_X;
break; break;
case 'y': case 'y':
mem_type = MEM_Y; mem_type = MEM_Y;
break; break;
case 'p': case 'p':
mem_type = MEM_P; mem_type = MEM_P;
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
if (CMD_ARGC < 2) if (CMD_ARGC < 2)
@@ -2026,35 +2025,35 @@ COMMAND_HANDLER(dsp563xx_add_watchpoint_command)
enum watchpoint_condition cond; enum watchpoint_condition cond;
switch (CMD_ARGV[0][0]) { switch (CMD_ARGV[0][0]) {
case '>': case '>':
cond = GREATER; cond = GREATER;
break; break;
case '<': case '<':
cond = LESS_THAN; cond = LESS_THAN;
break; break;
case '=': case '=':
cond = EQUAL; cond = EQUAL;
break; break;
case '!': case '!':
cond = NOT_EQUAL; cond = NOT_EQUAL;
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
enum watchpoint_rw rw; enum watchpoint_rw rw;
switch (CMD_ARGV[1][0]) { switch (CMD_ARGV[1][0]) {
case 'r': case 'r':
rw = WPT_READ; rw = WPT_READ;
break; break;
case 'w': case 'w':
rw = WPT_WRITE; rw = WPT_WRITE;
break; break;
case 'a': case 'a':
rw = WPT_ACCESS; rw = WPT_ACCESS;
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
err = dsp563xx_add_custom_watchpoint(target, address, mem_type, rw, cond); err = dsp563xx_add_custom_watchpoint(target, address, mem_type, rw, cond);
@@ -2095,28 +2094,28 @@ COMMAND_HANDLER(dsp563xx_mem_command)
uint8_t *buffer, *b; uint8_t *buffer, *b;
switch (CMD_NAME[1]) { switch (CMD_NAME[1]) {
case 'w': case 'w':
read_mem = 0; read_mem = 0;
break; break;
case 'd': case 'd':
read_mem = 1; read_mem = 1;
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
switch (CMD_NAME[3]) { switch (CMD_NAME[3]) {
case 'x': case 'x':
mem_type = MEM_X; mem_type = MEM_X;
break; break;
case 'y': case 'y':
mem_type = MEM_Y; mem_type = MEM_Y;
break; break;
case 'p': case 'p':
mem_type = MEM_P; mem_type = MEM_P;
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
if (CMD_ARGC > 0) if (CMD_ARGC > 0)

124
src/target/embeddedice.c
View File

@@ -219,69 +219,69 @@ struct reg_cache *embeddedice_build_reg_cache(struct target *target,
LOG_INFO("Embedded ICE version %d", eice_version); LOG_INFO("Embedded ICE version %d", eice_version);
switch (eice_version) { switch (eice_version) {
case 1: case 1:
/* ARM7TDMI r3, ARM7TDMI-S r3 /* ARM7TDMI r3, ARM7TDMI-S r3
* *
* REVISIT docs say ARM7TDMI-S r4 uses version 1 but * REVISIT docs say ARM7TDMI-S r4 uses version 1 but
* that it has 6-bit CTRL and 5-bit STAT... doc bug? * that it has 6-bit CTRL and 5-bit STAT... doc bug?
* ARM7TDMI r4 docs say EICE v4. * ARM7TDMI r4 docs say EICE v4.
*/ */
reg_list[EICE_DBG_CTRL].size = 3; reg_list[EICE_DBG_CTRL].size = 3;
reg_list[EICE_DBG_STAT].size = 5; reg_list[EICE_DBG_STAT].size = 5;
break;
case 2:
/* ARM9TDMI */
reg_list[EICE_DBG_CTRL].size = 4;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
break;
case 3:
LOG_ERROR("EmbeddedICE v%d handling might be broken",
eice_version);
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
arm7_9->has_monitor_mode = 1;
break;
case 4:
/* ARM7TDMI r4 */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1;
break;
case 5:
/* ARM9E-S rev 1 */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
arm7_9->has_monitor_mode = 1;
break;
case 6:
/* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 10;
/* DBG_STAT has MOE bits */
arm7_9->has_monitor_mode = 1;
break;
case 7:
LOG_ERROR("EmbeddedICE v%d handling might be broken",
eice_version);
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1;
break;
default:
/*
* The Feroceon implementation has the version number
* in some unusual bits. Let feroceon.c validate it
* and do the appropriate setup itself.
*/
if (strcmp(target_type_name(target), "feroceon") == 0 ||
strcmp(target_type_name(target), "dragonite") == 0)
break; break;
case 2: LOG_ERROR("unknown EmbeddedICE version "
/* ARM9TDMI */ "(comms ctrl: 0x%8.8" PRIx32 ")",
reg_list[EICE_DBG_CTRL].size = 4; buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
break;
case 3:
LOG_ERROR("EmbeddedICE v%d handling might be broken",
eice_version);
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
arm7_9->has_monitor_mode = 1;
break;
case 4:
/* ARM7TDMI r4 */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1;
break;
case 5:
/* ARM9E-S rev 1 */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
arm7_9->has_monitor_mode = 1;
break;
case 6:
/* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 10;
/* DBG_STAT has MOE bits */
arm7_9->has_monitor_mode = 1;
break;
case 7:
LOG_ERROR("EmbeddedICE v%d handling might be broken",
eice_version);
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1;
break;
default:
/*
* The Feroceon implementation has the version number
* in some unusual bits. Let feroceon.c validate it
* and do the appropriate setup itself.
*/
if (strcmp(target_type_name(target), "feroceon") == 0 ||
strcmp(target_type_name(target), "dragonite") == 0)
break;
LOG_ERROR("unknown EmbeddedICE version "
"(comms ctrl: 0x%8.8" PRIx32 ")",
buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
} }
/* On Feroceon and Dragonite the second unit is seemingly missing. */ /* On Feroceon and Dragonite the second unit is seemingly missing. */

166
src/target/esirisc.c
View File

@@ -367,24 +367,24 @@ static int esirisc_read_memory(struct target *target, target_addr_t address,
void *value_p; void *value_p;
switch (size) { switch (size) {
case sizeof(value.word): case sizeof(value.word):
value_p = &value.word; value_p = &value.word;
retval = esirisc_jtag_read_word(jtag_info, address, value_p); retval = esirisc_jtag_read_word(jtag_info, address, value_p);
break; break;
case sizeof(value.hword): case sizeof(value.hword):
value_p = &value.hword; value_p = &value.hword;
retval = esirisc_jtag_read_hword(jtag_info, address, value_p); retval = esirisc_jtag_read_hword(jtag_info, address, value_p);
break; break;
case sizeof(value.byte): case sizeof(value.byte):
value_p = &value.byte; value_p = &value.byte;
retval = esirisc_jtag_read_byte(jtag_info, address, value_p); retval = esirisc_jtag_read_byte(jtag_info, address, value_p);
break; break;
default: default:
LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size); LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size);
return ERROR_FAIL; return ERROR_FAIL;
} }
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
@@ -415,24 +415,24 @@ static int esirisc_write_memory(struct target *target, target_addr_t address,
union esirisc_memory value; union esirisc_memory value;
switch (size) { switch (size) {
case sizeof(value.word): case sizeof(value.word):
value.word = buf_get_u32(buffer, 0, num_bits); value.word = buf_get_u32(buffer, 0, num_bits);
retval = esirisc_jtag_write_word(jtag_info, address, value.word); retval = esirisc_jtag_write_word(jtag_info, address, value.word);
break; break;
case sizeof(value.hword): case sizeof(value.hword):
value.hword = buf_get_u32(buffer, 0, num_bits); value.hword = buf_get_u32(buffer, 0, num_bits);
retval = esirisc_jtag_write_hword(jtag_info, address, value.hword); retval = esirisc_jtag_write_hword(jtag_info, address, value.hword);
break; break;
case sizeof(value.byte): case sizeof(value.byte):
value.byte = buf_get_u32(buffer, 0, num_bits); value.byte = buf_get_u32(buffer, 0, num_bits);
retval = esirisc_jtag_write_byte(jtag_info, address, value.byte); retval = esirisc_jtag_write_byte(jtag_info, address, value.byte);
break; break;
default: default:
LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size); LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size);
return ERROR_FAIL; return ERROR_FAIL;
} }
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
@@ -641,25 +641,25 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
uint32_t sn; uint32_t sn;
switch (watchpoint->length) { switch (watchpoint->length) {
case sizeof(uint64_t): case sizeof(uint64_t):
sn = 0x3; sn = 0x3;
break; break;
case sizeof(uint32_t): case sizeof(uint32_t):
sn = 0x2; sn = 0x2;
break; break;
case sizeof(uint16_t): case sizeof(uint16_t):
sn = 0x1; sn = 0x1;
break; break;
case sizeof(uint8_t): case sizeof(uint8_t):
sn = 0x0; sn = 0x0;
break; break;
default: default:
LOG_TARGET_ERROR(target, "unsupported length: %" PRIu32, LOG_TARGET_ERROR(target, "unsupported length: %" PRIu32,
watchpoint->length); watchpoint->length);
return ERROR_FAIL; return ERROR_FAIL;
} }
dbs |= (sn << (2 * wp_index)); /* DBS.Sn */ dbs |= (sn << (2 * wp_index)); /* DBS.Sn */
@@ -679,21 +679,21 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc
uint32_t dn; uint32_t dn;
switch (watchpoint->rw) { switch (watchpoint->rw) {
case WPT_READ: case WPT_READ:
dn = 0x1; dn = 0x1;
break; break;
case WPT_WRITE: case WPT_WRITE:
dn = 0x2; dn = 0x2;
break; break;
case WPT_ACCESS: case WPT_ACCESS:
dn = 0x3; dn = 0x3;
break; break;
default: default:
LOG_TARGET_ERROR(target, "unsupported rw: %" PRId32, watchpoint->rw); LOG_TARGET_ERROR(target, "unsupported rw: %" PRId32, watchpoint->rw);
return ERROR_FAIL; return ERROR_FAIL;
} }
dbc |= (dn << (2 * wp_index)); /* DBC.Dn */ dbc |= (dn << (2 * wp_index)); /* DBC.Dn */
@@ -1046,33 +1046,33 @@ static int esirisc_debug_entry(struct target *target)
uint32_t eid = buf_get_u32(esirisc->eid->value, 0, esirisc->eid->size); uint32_t eid = buf_get_u32(esirisc->eid->value, 0, esirisc->eid->size);
switch (eid) { switch (eid) {
/* /*
* InstBreakpoint exceptions are also raised when a core is * InstBreakpoint exceptions are also raised when a core is
* halted for debugging. The following is required to * halted for debugging. The following is required to
* determine if a breakpoint was encountered. * determine if a breakpoint was encountered.
*/ */
case EID_INST_BREAKPOINT: case EID_INST_BREAKPOINT:
breakpoint = breakpoint_find(target, breakpoint = breakpoint_find(target,
buf_get_u32(esirisc->epc->value, 0, esirisc->epc->size)); buf_get_u32(esirisc->epc->value, 0, esirisc->epc->size));
target->debug_reason = (breakpoint) ? target->debug_reason = (breakpoint) ?
DBG_REASON_BREAKPOINT : DBG_REASON_DBGRQ; DBG_REASON_BREAKPOINT : DBG_REASON_DBGRQ;
break; break;
/* /*
* eSi-RISC treats watchpoints similarly to breakpoints, * eSi-RISC treats watchpoints similarly to breakpoints,
* however GDB will not request to step over the current * however GDB will not request to step over the current
* instruction when a watchpoint fires. The following is * instruction when a watchpoint fires. The following is
* required to resume the target. * required to resume the target.
*/ */
case EID_DATA_BREAKPOINT: case EID_DATA_BREAKPOINT:
esirisc_remove_watchpoints(target); esirisc_remove_watchpoints(target);
esirisc_debug_step(target); esirisc_debug_step(target);
esirisc_add_watchpoints(target); esirisc_add_watchpoints(target);
target->debug_reason = DBG_REASON_WATCHPOINT; target->debug_reason = DBG_REASON_WATCHPOINT;
break; break;
default: default:
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
} }
} }

159
src/target/esirisc_trace.c
View File

@@ -389,84 +389,87 @@ static int esirisc_trace_analyze_full(struct command_invocation *cmd, uint8_t *b
goto fail; goto fail;
switch (id) { switch (id) {
case ESIRISC_TRACE_ID_EXECUTE: case ESIRISC_TRACE_ID_EXECUTE:
case ESIRISC_TRACE_ID_STALL: case ESIRISC_TRACE_ID_STALL:
case ESIRISC_TRACE_ID_BRANCH: case ESIRISC_TRACE_ID_BRANCH:
command_print(cmd, "%s", esirisc_trace_id_strings[id]); command_print(cmd, "%s", esirisc_trace_id_strings[id]);
break;
case ESIRISC_TRACE_ID_EXTENDED: {
uint32_t ext_id;
retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 4, &ext_id);
if (retval != ERROR_OK)
goto fail;
switch (ext_id) {
case ESIRISC_TRACE_EXT_ID_STOP:
case ESIRISC_TRACE_EXT_ID_WAIT:
case ESIRISC_TRACE_EXT_ID_MULTICYCLE:
command_print(cmd, "%s", esirisc_trace_ext_id_strings[ext_id]);
break; break;
case ESIRISC_TRACE_ID_EXTENDED: { case ESIRISC_TRACE_EXT_ID_ERET:
uint32_t ext_id; case ESIRISC_TRACE_EXT_ID_PC:
case ESIRISC_TRACE_EXT_ID_INDIRECT:
case ESIRISC_TRACE_EXT_ID_END_PC: {
uint32_t pc;
retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 4, &ext_id); retval = esirisc_trace_buf_get_pc(target, buffer, size, &pos, &pc);
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto fail; goto fail;
switch (ext_id) { command_print(cmd, "%s PC: 0x%" PRIx32,
case ESIRISC_TRACE_EXT_ID_STOP: esirisc_trace_ext_id_strings[ext_id], pc);
case ESIRISC_TRACE_EXT_ID_WAIT:
case ESIRISC_TRACE_EXT_ID_MULTICYCLE:
command_print(cmd, "%s", esirisc_trace_ext_id_strings[ext_id]);
break;
case ESIRISC_TRACE_EXT_ID_ERET: if (ext_id == ESIRISC_TRACE_EXT_ID_END_PC) {
case ESIRISC_TRACE_EXT_ID_PC: command_print(cmd, "--- end of trace ---");
case ESIRISC_TRACE_EXT_ID_INDIRECT: return ERROR_OK;
case ESIRISC_TRACE_EXT_ID_END_PC: {
uint32_t pc;
retval = esirisc_trace_buf_get_pc(target, buffer, size, &pos, &pc);
if (retval != ERROR_OK)
goto fail;
command_print(cmd, "%s PC: 0x%" PRIx32,
esirisc_trace_ext_id_strings[ext_id], pc);
if (ext_id == ESIRISC_TRACE_EXT_ID_END_PC) {
command_print(cmd, "--- end of trace ---");
return ERROR_OK;
}
break;
}
case ESIRISC_TRACE_EXT_ID_EXCEPTION: {
uint32_t eid, epc;
retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 6, &eid);
if (retval != ERROR_OK)
goto fail;
retval = esirisc_trace_buf_get_pc(target, buffer, size, &pos, &epc);
if (retval != ERROR_OK)
goto fail;
command_print(cmd, "%s EID: 0x%" PRIx32 ", EPC: 0x%" PRIx32,
esirisc_trace_ext_id_strings[ext_id], eid, epc);
break;
}
case ESIRISC_TRACE_EXT_ID_COUNT: {
uint32_t count;
retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 6, &count);
if (retval != ERROR_OK)
goto fail;
command_print(cmd, "repeats %" PRIu32 " %s", count,
(count == 1) ? "time" : "times");
break;
}
case ESIRISC_TRACE_EXT_ID_END:
command_print(cmd, "--- end of trace ---");
return ERROR_OK;
default:
command_print(cmd, "invalid extended trace ID: %" PRIu32, ext_id);
return ERROR_FAIL;
} }
break; break;
} }
case ESIRISC_TRACE_EXT_ID_EXCEPTION: {
uint32_t eid, epc;
retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 6, &eid);
if (retval != ERROR_OK)
goto fail;
retval = esirisc_trace_buf_get_pc(target, buffer, size, &pos, &epc);
if (retval != ERROR_OK)
goto fail;
command_print(cmd, "%s EID: 0x%" PRIx32 ", EPC: 0x%" PRIx32,
esirisc_trace_ext_id_strings[ext_id], eid, epc);
break;
}
case ESIRISC_TRACE_EXT_ID_COUNT: {
uint32_t count;
retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 6, &count);
if (retval != ERROR_OK)
goto fail;
command_print(cmd, "repeats %" PRIu32 " %s", count,
(count == 1) ? "time" : "times");
break;
}
case ESIRISC_TRACE_EXT_ID_END:
command_print(cmd, "--- end of trace ---");
return ERROR_OK;
default: default:
command_print(cmd, "invalid trace ID: %" PRIu32, id); command_print(cmd, "invalid extended trace ID: %" PRIu32, ext_id);
return ERROR_FAIL; return ERROR_FAIL;
}
break;
}
default:
command_print(cmd, "invalid trace ID: %" PRIu32, id);
return ERROR_FAIL;
} }
} }
@@ -511,21 +514,21 @@ static int esirisc_trace_analyze(struct command_invocation *cmd, uint8_t *buffer
struct esirisc_trace *trace_info = &esirisc->trace_info; struct esirisc_trace *trace_info = &esirisc->trace_info;
switch (trace_info->format) { switch (trace_info->format) {
case ESIRISC_TRACE_FORMAT_FULL: case ESIRISC_TRACE_FORMAT_FULL:
command_print(cmd, "--- full pipeline ---"); command_print(cmd, "--- full pipeline ---");
return esirisc_trace_analyze_full(cmd, buffer, size); return esirisc_trace_analyze_full(cmd, buffer, size);
case ESIRISC_TRACE_FORMAT_BRANCH: case ESIRISC_TRACE_FORMAT_BRANCH:
command_print(cmd, "--- branches taken ---"); command_print(cmd, "--- branches taken ---");
return esirisc_trace_analyze_full(cmd, buffer, size); return esirisc_trace_analyze_full(cmd, buffer, size);
case ESIRISC_TRACE_FORMAT_ICACHE: case ESIRISC_TRACE_FORMAT_ICACHE:
command_print(cmd, "--- icache misses ---"); command_print(cmd, "--- icache misses ---");
return esirisc_trace_analyze_simple(cmd, buffer, size); return esirisc_trace_analyze_simple(cmd, buffer, size);
default: default:
command_print(cmd, "invalid trace format: %i", trace_info->format); command_print(cmd, "invalid trace format: %i", trace_info->format);
return ERROR_FAIL; return ERROR_FAIL;
} }
} }

364
src/target/etm.c
View File

@@ -326,24 +326,24 @@ struct reg_cache *etm_build_reg_cache(struct target *target,
} else { } else {
switch (config >> 28) { switch (config >> 28) {
case 7: case 7:
case 5: case 5:
case 3: case 3:
bcd_vers = 0x13; bcd_vers = 0x13;
break; break;
case 4: case 4:
case 2: case 2:
bcd_vers = 0x12; bcd_vers = 0x12;
break; break;
case 1: case 1:
bcd_vers = 0x11; bcd_vers = 0x11;
break; break;
case 0: case 0:
bcd_vers = 0x10; bcd_vers = 0x10;
break; break;
default: default:
LOG_WARNING("Bad ETMv1 protocol %d", config >> 28); LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
goto fail; goto fail;
} }
} }
etm_ctx->bcd_vers = bcd_vers; etm_ctx->bcd_vers = bcd_vers;
@@ -923,48 +923,48 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
ctx->pipe_index += 2; ctx->pipe_index += 2;
switch (ctx->last_branch_reason) { switch (ctx->last_branch_reason) {
case 0x0: /* normal PC change */ case 0x0: /* normal PC change */
next_pc = ctx->last_branch; next_pc = ctx->last_branch;
break; break;
case 0x1: /* tracing enabled */ case 0x1: /* tracing enabled */
command_print(cmd,
"--- tracing enabled at 0x%8.8" PRIx32 " ---",
ctx->last_branch);
ctx->current_pc = ctx->last_branch;
ctx->pipe_index++;
continue;
case 0x2: /* trace restarted after FIFO overflow */
command_print(cmd,
"--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---",
ctx->last_branch);
ctx->current_pc = ctx->last_branch;
ctx->pipe_index++;
continue;
case 0x3: /* exit from debug state */
command_print(cmd,
"--- exit from debug state at 0x%8.8" PRIx32 " ---",
ctx->last_branch);
ctx->current_pc = ctx->last_branch;
ctx->pipe_index++;
continue;
case 0x4: /* periodic synchronization point */
next_pc = ctx->last_branch;
/* if we had no valid PC prior to this synchronization point,
* we have to move on with the next trace cycle
*/
if (!current_pc_ok) {
command_print(cmd, command_print(cmd,
"--- tracing enabled at 0x%8.8" PRIx32 " ---", "--- periodic synchronization point at 0x%8.8" PRIx32 " ---",
ctx->last_branch); next_pc);
ctx->current_pc = ctx->last_branch; ctx->current_pc = next_pc;
ctx->pipe_index++; ctx->pipe_index++;
continue; continue;
case 0x2: /* trace restarted after FIFO overflow */ }
command_print(cmd, break;
"--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", default: /* reserved */
ctx->last_branch); LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved",
ctx->current_pc = ctx->last_branch; ctx->last_branch_reason);
ctx->pipe_index++; return ERROR_FAIL;
continue;
case 0x3: /* exit from debug state */
command_print(cmd,
"--- exit from debug state at 0x%8.8" PRIx32 " ---",
ctx->last_branch);
ctx->current_pc = ctx->last_branch;
ctx->pipe_index++;
continue;
case 0x4: /* periodic synchronization point */
next_pc = ctx->last_branch;
/* if we had no valid PC prior to this synchronization point,
* we have to move on with the next trace cycle
*/
if (!current_pc_ok) {
command_print(cmd,
"--- periodic synchronization point at 0x%8.8" PRIx32 " ---",
next_pc);
ctx->current_pc = next_pc;
ctx->pipe_index++;
continue;
}
break;
default: /* reserved */
LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved",
ctx->last_branch_reason);
return ERROR_FAIL;
} }
/* if we got here the branch was a normal PC change /* if we got here the branch was a normal PC change
@@ -1144,21 +1144,21 @@ static COMMAND_HELPER(handle_etm_tracemode_command_update,
uint8_t context_id; uint8_t context_id;
COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id); COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
switch (context_id) { switch (context_id) {
case 0: case 0:
tracemode |= ETM_CTRL_CONTEXTID_NONE; tracemode |= ETM_CTRL_CONTEXTID_NONE;
break; break;
case 8: case 8:
tracemode |= ETM_CTRL_CONTEXTID_8; tracemode |= ETM_CTRL_CONTEXTID_8;
break; break;
case 16: case 16:
tracemode |= ETM_CTRL_CONTEXTID_16; tracemode |= ETM_CTRL_CONTEXTID_16;
break; break;
case 32: case 32:
tracemode |= ETM_CTRL_CONTEXTID_32; tracemode |= ETM_CTRL_CONTEXTID_32;
break; break;
default: default:
command_print(CMD, "invalid option '%s'", CMD_ARGV[1]); command_print(CMD, "invalid option '%s'", CMD_ARGV[1]);
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
bool etmv1_cycle_accurate; bool etmv1_cycle_accurate;
@@ -1201,14 +1201,14 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
uint32_t tracemode = etm->control; uint32_t tracemode = etm->control;
switch (CMD_ARGC) { switch (CMD_ARGC) {
case 0: case 0:
break; break;
case 4: case 4:
CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
&tracemode); &tracemode);
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
/** /**
@@ -1219,33 +1219,33 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
command_print(CMD, "current tracemode configuration:"); command_print(CMD, "current tracemode configuration:");
switch (tracemode & ETM_CTRL_TRACE_MASK) { switch (tracemode & ETM_CTRL_TRACE_MASK) {
default: default:
command_print(CMD, "data tracing: none"); command_print(CMD, "data tracing: none");
break; break;
case ETM_CTRL_TRACE_DATA: case ETM_CTRL_TRACE_DATA:
command_print(CMD, "data tracing: data only"); command_print(CMD, "data tracing: data only");
break; break;
case ETM_CTRL_TRACE_ADDR: case ETM_CTRL_TRACE_ADDR:
command_print(CMD, "data tracing: address only"); command_print(CMD, "data tracing: address only");
break; break;
case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR: case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
command_print(CMD, "data tracing: address and data"); command_print(CMD, "data tracing: address and data");
break; break;
} }
switch (tracemode & ETM_CTRL_CONTEXTID_MASK) { switch (tracemode & ETM_CTRL_CONTEXTID_MASK) {
case ETM_CTRL_CONTEXTID_NONE: case ETM_CTRL_CONTEXTID_NONE:
command_print(CMD, "contextid tracing: none"); command_print(CMD, "contextid tracing: none");
break; break;
case ETM_CTRL_CONTEXTID_8: case ETM_CTRL_CONTEXTID_8:
command_print(CMD, "contextid tracing: 8 bit"); command_print(CMD, "contextid tracing: 8 bit");
break; break;
case ETM_CTRL_CONTEXTID_16: case ETM_CTRL_CONTEXTID_16:
command_print(CMD, "contextid tracing: 16 bit"); command_print(CMD, "contextid tracing: 16 bit");
break; break;
case ETM_CTRL_CONTEXTID_32: case ETM_CTRL_CONTEXTID_32:
command_print(CMD, "contextid tracing: 32 bit"); command_print(CMD, "contextid tracing: 32 bit");
break; break;
} }
if (tracemode & ETM_CTRL_CYCLE_ACCURATE) if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
@@ -1333,39 +1333,39 @@ COMMAND_HANDLER(handle_etm_config_command)
uint8_t port_width; uint8_t port_width;
COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width); COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
switch (port_width) { switch (port_width) {
/* before ETMv3.0 */ /* before ETMv3.0 */
case 4: case 4:
portmode |= ETM_PORT_4BIT; portmode |= ETM_PORT_4BIT;
break; break;
case 8: case 8:
portmode |= ETM_PORT_8BIT; portmode |= ETM_PORT_8BIT;
break; break;
case 16: case 16:
portmode |= ETM_PORT_16BIT; portmode |= ETM_PORT_16BIT;
break; break;
/* ETMv3.0 and later*/ /* ETMv3.0 and later*/
case 24: case 24:
portmode |= ETM_PORT_24BIT; portmode |= ETM_PORT_24BIT;
break; break;
case 32: case 32:
portmode |= ETM_PORT_32BIT; portmode |= ETM_PORT_32BIT;
break; break;
case 48: case 48:
portmode |= ETM_PORT_48BIT; portmode |= ETM_PORT_48BIT;
break; break;
case 64: case 64:
portmode |= ETM_PORT_64BIT; portmode |= ETM_PORT_64BIT;
break; break;
case 1: case 1:
portmode |= ETM_PORT_1BIT; portmode |= ETM_PORT_1BIT;
break; break;
case 2: case 2:
portmode |= ETM_PORT_2BIT; portmode |= ETM_PORT_2BIT;
break; break;
default: default:
command_print(CMD, command_print(CMD,
"unsupported ETM port width '%s'", CMD_ARGV[1]); "unsupported ETM port width '%s'", CMD_ARGV[1]);
return ERROR_FAIL; return ERROR_FAIL;
} }
if (strcmp("normal", CMD_ARGV[2]) == 0) if (strcmp("normal", CMD_ARGV[2]) == 0)
@@ -1496,38 +1496,38 @@ COMMAND_HANDLER(handle_etm_info_command)
if (etm->bcd_vers >= 0x30) if (etm->bcd_vers >= 0x30)
max_port_size |= (config >> 6) & 0x08; max_port_size |= (config >> 6) & 0x08;
switch (max_port_size) { switch (max_port_size) {
/* before ETMv3.0 */ /* before ETMv3.0 */
case 0: case 0:
max_port_size = 4; max_port_size = 4;
break; break;
case 1: case 1:
max_port_size = 8; max_port_size = 8;
break; break;
case 2: case 2:
max_port_size = 16; max_port_size = 16;
break; break;
/* ETMv3.0 and later*/ /* ETMv3.0 and later*/
case 3: case 3:
max_port_size = 24; max_port_size = 24;
break; break;
case 4: case 4:
max_port_size = 32; max_port_size = 32;
break; break;
case 5: case 5:
max_port_size = 48; max_port_size = 48;
break; break;
case 6: case 6:
max_port_size = 64; max_port_size = 64;
break; break;
case 8: case 8:
max_port_size = 1; max_port_size = 1;
break; break;
case 9: case 9:
max_port_size = 2; max_port_size = 2;
break; break;
default: default:
LOG_ERROR("Illegal max_port_size"); LOG_ERROR("Illegal max_port_size");
return ERROR_FAIL; return ERROR_FAIL;
} }
command_print(CMD, "max. port size: %i", max_port_size); command_print(CMD, "max. port size: %i", max_port_size);
@@ -1966,19 +1966,19 @@ COMMAND_HANDLER(handle_etm_analyze_command)
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
/* FIX! error should be reported inside etmv1_analyze_trace() */ /* FIX! error should be reported inside etmv1_analyze_trace() */
switch (retval) { switch (retval) {
case ERROR_ETM_ANALYSIS_FAILED: case ERROR_ETM_ANALYSIS_FAILED:
command_print(CMD, command_print(CMD,
"further analysis failed (corrupted trace data or just end of data"); "further analysis failed (corrupted trace data or just end of data");
break; break;
case ERROR_TRACE_INSTRUCTION_UNAVAILABLE: case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
command_print(CMD, command_print(CMD,
"no instruction for current address available, analysis aborted"); "no instruction for current address available, analysis aborted");
break; break;
case ERROR_TRACE_IMAGE_UNAVAILABLE: case ERROR_TRACE_IMAGE_UNAVAILABLE:
command_print(CMD, "no image available for trace analysis"); command_print(CMD, "no image available for trace analysis");
break; break;
default: default:
command_print(CMD, "unknown error"); command_print(CMD, "unknown error");
} }
} }

18
src/target/fa526.c
View File

@@ -80,15 +80,15 @@ static void fa526_read_core_regs_target_buffer(struct target *target,
if (mask & (1 << i)) if (mask & (1 << i))
/* nothing fetched, STM in MEMORY (i'th cycle) */ /* nothing fetched, STM in MEMORY (i'th cycle) */
switch (size) { switch (size) {
case 4: case 4:
arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
break; break;
case 2: case 2:
arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
break; break;
case 1: case 1:
arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
break; break;
} }
} }
} }

18
src/target/feroceon.c
View File

@@ -191,15 +191,15 @@ static void feroceon_read_core_regs_target_buffer(struct target *target,
for (i = 0; i <= 15; i++) { for (i = 0; i <= 15; i++) {
if (mask & (1 << i)) { if (mask & (1 << i)) {
switch (size) { switch (size) {
case 4: case 4:
arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
break; break;
case 2: case 2:
arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
break; break;
case 1: case 1:
arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
break; break;
} }
} }
} }

55
src/target/image.c
View File

@@ -815,36 +815,35 @@ static int image_mot_buffer_complete_inner(struct image *image,
} }
} else if (record_type >= 1 && record_type <= 3) { } else if (record_type >= 1 && record_type <= 3) {
switch (record_type) { switch (record_type) {
case 1: case 1:
/* S1 - 16 bit address data record */ /* S1 - 16 bit address data record */
sscanf(&lpsz_line[bytes_read], "%4" SCNx32, &address); sscanf(&lpsz_line[bytes_read], "%4" SCNx32, &address);
cal_checksum += (uint8_t)(address >> 8); cal_checksum += (uint8_t)(address >> 8);
cal_checksum += (uint8_t)address; cal_checksum += (uint8_t)address;
bytes_read += 4; bytes_read += 4;
count -= 2; count -= 2;
break; break;
case 2: case 2:
/* S2 - 24 bit address data record */ /* S2 - 24 bit address data record */
sscanf(&lpsz_line[bytes_read], "%6" SCNx32, &address); sscanf(&lpsz_line[bytes_read], "%6" SCNx32, &address);
cal_checksum += (uint8_t)(address >> 16); cal_checksum += (uint8_t)(address >> 16);
cal_checksum += (uint8_t)(address >> 8); cal_checksum += (uint8_t)(address >> 8);
cal_checksum += (uint8_t)address; cal_checksum += (uint8_t)address;
bytes_read += 6; bytes_read += 6;
count -= 3; count -= 3;
break; break;
case 3:
/* S3 - 32 bit address data record */
sscanf(&lpsz_line[bytes_read], "%8" SCNx32, &address);
cal_checksum += (uint8_t)(address >> 24);
cal_checksum += (uint8_t)(address >> 16);
cal_checksum += (uint8_t)(address >> 8);
cal_checksum += (uint8_t)address;
bytes_read += 8;
count -= 4;
break;
case 3:
/* S3 - 32 bit address data record */
sscanf(&lpsz_line[bytes_read], "%8" SCNx32, &address);
cal_checksum += (uint8_t)(address >> 24);
cal_checksum += (uint8_t)(address >> 16);
cal_checksum += (uint8_t)(address >> 8);
cal_checksum += (uint8_t)address;
bytes_read += 8;
count -= 4;
break;
} }
if (full_address != address) { if (full_address != address) {

95
src/target/mips32.c
View File

@@ -1687,26 +1687,25 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
} }
switch (CMD_ARGC) { switch (CMD_ARGC) {
case 0: /* No arg => print out all cp0 regs */ case 0: /* No arg => print out all cp0 regs */
retval = mips32_cp0_get_all_regs(CMD, ejtag_info, mips32->cp0_mask); retval = mips32_cp0_get_all_regs(CMD, ejtag_info, mips32->cp0_mask);
break; break;
case 1: /* 1 arg => get cp0 #reg/#sel value by name */ case 1: /* 1 arg => get cp0 #reg/#sel value by name */
retval = mips32_cp0_get_reg_by_name(CMD, ejtag_info, mips32->cp0_mask); retval = mips32_cp0_get_reg_by_name(CMD, ejtag_info, mips32->cp0_mask);
break; break;
case 2: /* 2 args => get cp0 reg/sel value or set value by name */ case 2: /* 2 args => get cp0 reg/sel value or set value by name */
tmp = *CMD_ARGV[0]; tmp = *CMD_ARGV[0];
if (isdigit(tmp)) /* starts from number then args are #reg and #sel */ if (isdigit(tmp)) /* starts from number then args are #reg and #sel */
retval = mips32_cp0_get_reg_by_number(CMD, ejtag_info); retval = mips32_cp0_get_reg_by_number(CMD, ejtag_info);
else /* or set value by register name */ else /* or set value by register name */
retval = mips32_cp0_set_reg_by_name(CMD, mips32, ejtag_info); retval = mips32_cp0_set_reg_by_name(CMD, mips32, ejtag_info);
break;
break; case 3: /* 3 args => set cp0 reg/sel value*/
case 3: /* 3 args => set cp0 reg/sel value*/ retval = mips32_cp0_set_reg_by_number(CMD, mips32, ejtag_info);
retval = mips32_cp0_set_reg_by_number(CMD, mips32, ejtag_info); break;
break; default: /* Other argc => err */
default: /* Other argc => err */ retval = ERROR_COMMAND_SYNTAX_ERROR;
retval = ERROR_COMMAND_SYNTAX_ERROR; break;
break;
} }
return retval; return retval;
@@ -2003,20 +2002,20 @@ COMMAND_HANDLER(mips32_handle_cpuinfo_command)
uint32_t mmu_type = (config0 >> 7) & 7; /* MMU Type Info */ uint32_t mmu_type = (config0 >> 7) & 7; /* MMU Type Info */
char *mmu; char *mmu;
switch (mmu_type) { switch (mmu_type) {
case MIPS32_MMU_TLB: case MIPS32_MMU_TLB:
mmu = "TLB"; mmu = "TLB";
break; break;
case MIPS32_MMU_BAT: case MIPS32_MMU_BAT:
mmu = "BAT"; mmu = "BAT";
break; break;
case MIPS32_MMU_FIXED: case MIPS32_MMU_FIXED:
mmu = "FIXED"; mmu = "FIXED";
break; break;
case MIPS32_MMU_DUAL_VTLB_FTLB: case MIPS32_MMU_DUAL_VTLB_FTLB:
mmu = "DUAL VAR/FIXED"; mmu = "DUAL VAR/FIXED";
break; break;
default: default:
mmu = "Unknown"; mmu = "Unknown";
} }
command_print(CMD, "MMU Type: %s", mmu); command_print(CMD, "MMU Type: %s", mmu);
@@ -2262,25 +2261,25 @@ COMMAND_HANDLER(mips32_handle_dsp_command)
} }
switch (CMD_ARGC) { switch (CMD_ARGC) {
case 0: case 0:
retval = mips32_dsp_get_all_regs(CMD, mips32); retval = mips32_dsp_get_all_regs(CMD, mips32);
break; break;
case 1: case 1:
retval = mips32_dsp_get_register(CMD, mips32); retval = mips32_dsp_get_register(CMD, mips32);
break; break;
case 2: case 2:
tmp = *CMD_ARGV[0]; tmp = *CMD_ARGV[0];
if (isdigit(tmp)) { if (isdigit(tmp)) {
command_print(CMD, "Error: invalid dsp command format"); command_print(CMD, "Error: invalid dsp command format");
retval = ERROR_COMMAND_ARGUMENT_INVALID;
} else {
retval = mips32_dsp_set_register(CMD, mips32);
}
break;
default:
command_print(CMD, "Error: invalid argument format, required 0-2, given %d", CMD_ARGC);
retval = ERROR_COMMAND_ARGUMENT_INVALID; retval = ERROR_COMMAND_ARGUMENT_INVALID;
break; } else {
retval = mips32_dsp_set_register(CMD, mips32);
}
break;
default:
command_print(CMD, "Error: invalid argument format, required 0-2, given %d", CMD_ARGC);
retval = ERROR_COMMAND_ARGUMENT_INVALID;
break;
} }
return retval; return retval;
} }

48
src/target/mips32_dmaacc.c
View File

@@ -186,18 +186,18 @@ begin_ejtag_dma_read_b:
/* Handle the bigendian/littleendian */ /* Handle the bigendian/littleendian */
switch (addr & 0x3) { switch (addr & 0x3) {
case 0: case 0:
*data = v & 0xff; *data = v & 0xff;
break; break;
case 1: case 1:
*data = (v >> 8) & 0xff; *data = (v >> 8) & 0xff;
break; break;
case 2: case 2:
*data = (v >> 16) & 0xff; *data = (v >> 16) & 0xff;
break; break;
case 3: case 3:
*data = (v >> 24) & 0xff; *data = (v >> 24) & 0xff;
break; break;
} }
return ERROR_OK; return ERROR_OK;
@@ -341,12 +341,12 @@ begin_ejtag_dma_write_b:
int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf) int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
{ {
switch (size) { switch (size) {
case 1: case 1:
return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf); return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf);
case 2: case 2:
return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf); return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf);
case 4: case 4:
return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf); return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf);
} }
return ERROR_OK; return ERROR_OK;
@@ -397,12 +397,12 @@ static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr,
int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf) int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf)
{ {
switch (size) { switch (size) {
case 1: case 1:
return mips32_dmaacc_write_mem8(ejtag_info, addr, count, buf); return mips32_dmaacc_write_mem8(ejtag_info, addr, count, buf);
case 2: case 2:
return mips32_dmaacc_write_mem16(ejtag_info, addr, count, buf); return mips32_dmaacc_write_mem16(ejtag_info, addr, count, buf);
case 4: case 4:
return mips32_dmaacc_write_mem32(ejtag_info, addr, count, buf); return mips32_dmaacc_write_mem32(ejtag_info, addr, count, buf);
} }
return ERROR_OK; return ERROR_OK;

52
src/target/mips32_pracc.c
View File

@@ -819,19 +819,19 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz
mips32_cp0_read(ejtag_info, &conf, 16, 0); mips32_cp0_read(ejtag_info, &conf, 16, 0);
switch (KSEGX(addr)) { switch (KSEGX(addr)) {
case KUSEG: case KUSEG:
cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT; cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT;
break; break;
case KSEG0: case KSEG0:
cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT; cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT;
break; break;
case KSEG2: case KSEG2:
case KSEG3: case KSEG3:
cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT; cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT;
break; break;
default: default:
/* what ? */ /* what ? */
break; break;
} }
/** /**
@@ -1256,19 +1256,19 @@ static int mips32_pracc_fastdata_xfer_synchronize_cache(struct mips_ejtag *ejtag
mips32_cp0_read(ejtag_info, &conf, 16, 0); mips32_cp0_read(ejtag_info, &conf, 16, 0);
switch (KSEGX(addr)) { switch (KSEGX(addr)) {
case KUSEG: case KUSEG:
cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT; cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT;
break; break;
case KSEG0: case KSEG0:
cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT; cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT;
break; break;
case KSEG2: case KSEG2:
case KSEG3: case KSEG3:
cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT; cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT;
break; break;
default: default:
/* what ? */ /* what ? */
break; break;
} }
/** /**

66
src/target/mips_ejtag.c
View File

@@ -342,18 +342,18 @@ void ejtag_main_print_imp(struct mips_ejtag *ejtag_info)
EJTAG_IMP_HAS(EJTAG_IMP_MIPS64) ? " MIPS64" : " MIPS32"); EJTAG_IMP_HAS(EJTAG_IMP_MIPS64) ? " MIPS64" : " MIPS32");
switch (ejtag_info->ejtag_version) { switch (ejtag_info->ejtag_version) {
case EJTAG_VERSION_20: case EJTAG_VERSION_20:
ejtag_v20_print_imp(ejtag_info); ejtag_v20_print_imp(ejtag_info);
break; break;
case EJTAG_VERSION_25: case EJTAG_VERSION_25:
case EJTAG_VERSION_26: case EJTAG_VERSION_26:
case EJTAG_VERSION_31: case EJTAG_VERSION_31:
case EJTAG_VERSION_41: case EJTAG_VERSION_41:
case EJTAG_VERSION_51: case EJTAG_VERSION_51:
ejtag_v26_print_imp(ejtag_info); ejtag_v26_print_imp(ejtag_info);
break; break;
default: default:
break; break;
} }
} }
@@ -369,27 +369,27 @@ int mips_ejtag_init(struct mips_ejtag *ejtag_info)
ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07); ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
switch (ejtag_info->ejtag_version) { switch (ejtag_info->ejtag_version) {
case EJTAG_VERSION_20: case EJTAG_VERSION_20:
LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected"); LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
break; break;
case EJTAG_VERSION_25: case EJTAG_VERSION_25:
LOG_DEBUG("EJTAG: Version 2.5 Detected"); LOG_DEBUG("EJTAG: Version 2.5 Detected");
break; break;
case EJTAG_VERSION_26: case EJTAG_VERSION_26:
LOG_DEBUG("EJTAG: Version 2.6 Detected"); LOG_DEBUG("EJTAG: Version 2.6 Detected");
break; break;
case EJTAG_VERSION_31: case EJTAG_VERSION_31:
LOG_DEBUG("EJTAG: Version 3.1 Detected"); LOG_DEBUG("EJTAG: Version 3.1 Detected");
break; break;
case EJTAG_VERSION_41: case EJTAG_VERSION_41:
LOG_DEBUG("EJTAG: Version 4.1 Detected"); LOG_DEBUG("EJTAG: Version 4.1 Detected");
break; break;
case EJTAG_VERSION_51: case EJTAG_VERSION_51:
LOG_DEBUG("EJTAG: Version 5.1 Detected"); LOG_DEBUG("EJTAG: Version 5.1 Detected");
break; break;
default: default:
LOG_DEBUG("EJTAG: Unknown Version Detected"); LOG_DEBUG("EJTAG: Unknown Version Detected");
break; break;
} }
ejtag_main_print_imp(ejtag_info); ejtag_main_print_imp(ejtag_info);

22
src/target/mips_m4k.c
View File

@@ -893,17 +893,17 @@ static int mips_m4k_set_watchpoint(struct target *target,
} }
switch (watchpoint->rw) { switch (watchpoint->rw) {
case WPT_READ: case WPT_READ:
enable &= ~EJTAG_DBCN_NOLB; enable &= ~EJTAG_DBCN_NOLB;
break; break;
case WPT_WRITE: case WPT_WRITE:
enable &= ~EJTAG_DBCN_NOSB; enable &= ~EJTAG_DBCN_NOSB;
break; break;
case WPT_ACCESS: case WPT_ACCESS:
enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB); enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
break; break;
default: default:
LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
} }
watchpoint_set(watchpoint, wp_num); watchpoint_set(watchpoint, wp_num);

78
src/target/openrisc/jsp_server.c
View File

@@ -118,49 +118,49 @@ static int jsp_input(struct connection *connection)
buf_p = buffer; buf_p = buffer;
while (bytes_read) { while (bytes_read) {
switch (t_con->state) { switch (t_con->state) {
case TELNET_STATE_DATA: case TELNET_STATE_DATA:
if (*buf_p == 0xff) { if (*buf_p == 0xff) {
t_con->state = TELNET_STATE_IAC; t_con->state = TELNET_STATE_IAC;
} else { } else {
int out_len = 1; int out_len = 1;
int in_len; int in_len;
unsigned char in_buffer[10]; unsigned char in_buffer[10];
or1k_adv_jtag_jsp_xfer(jsp_service->jtag_info, or1k_adv_jtag_jsp_xfer(jsp_service->jtag_info,
&out_len, buf_p, &in_len, &out_len, buf_p, &in_len,
in_buffer); in_buffer);
if (in_len) if (in_len)
telnet_write(connection, in_buffer, in_len); telnet_write(connection, in_buffer, in_len);
} }
break;
case TELNET_STATE_IAC:
switch (*buf_p) {
case 0xfe:
t_con->state = TELNET_STATE_DONT;
break; break;
case TELNET_STATE_IAC: case 0xfd:
switch (*buf_p) { t_con->state = TELNET_STATE_DO;
case 0xfe:
t_con->state = TELNET_STATE_DONT;
break;
case 0xfd:
t_con->state = TELNET_STATE_DO;
break;
case 0xfc:
t_con->state = TELNET_STATE_WONT;
break;
case 0xfb:
t_con->state = TELNET_STATE_WILL;
break;
}
break; break;
case TELNET_STATE_SB: case 0xfc:
t_con->state = TELNET_STATE_WONT;
break; break;
case TELNET_STATE_SE: case 0xfb:
t_con->state = TELNET_STATE_WILL;
break; break;
case TELNET_STATE_WILL: }
case TELNET_STATE_WONT: break;
case TELNET_STATE_DO: case TELNET_STATE_SB:
case TELNET_STATE_DONT: break;
t_con->state = TELNET_STATE_DATA; case TELNET_STATE_SE:
break; break;
default: case TELNET_STATE_WILL:
LOG_ERROR("unknown telnet state"); case TELNET_STATE_WONT:
exit(-1); case TELNET_STATE_DO:
case TELNET_STATE_DONT:
t_con->state = TELNET_STATE_DATA;
break;
default:
LOG_ERROR("unknown telnet state");
exit(-1);
} }
bytes_read--; bytes_read--;

2467
src/target/semihosting_common.c
View File

File diff suppressed because it is too large Load Diff

48
src/target/stm8.c
View File

@@ -704,19 +704,19 @@ static int stm8_write_flash(struct target *target, enum mem_type type,
int res; int res;
switch (type) { switch (type) {
case (FLASH): case (FLASH):
stm8_unlock_flash(target); stm8_unlock_flash(target);
break; break;
case (EEPROM): case (EEPROM):
stm8_unlock_eeprom(target); stm8_unlock_eeprom(target);
break; break;
case (OPTION): case (OPTION):
stm8_unlock_eeprom(target); stm8_unlock_eeprom(target);
opt = OPT; opt = OPT;
break; break;
default: default:
LOG_ERROR("BUG: wrong mem_type %d", type); LOG_ERROR("BUG: wrong mem_type %d", type);
assert(0); assert(0);
} }
if (size == 2) { if (size == 2) {
@@ -1601,17 +1601,17 @@ static int stm8_set_watchpoint(struct target *target,
enum hw_break_type enable = 0; enum hw_break_type enable = 0;
switch (watchpoint->rw) { switch (watchpoint->rw) {
case WPT_READ: case WPT_READ:
enable = HWBRK_RD; enable = HWBRK_RD;
break; break;
case WPT_WRITE: case WPT_WRITE:
enable = HWBRK_WR; enable = HWBRK_WR;
break; break;
case WPT_ACCESS: case WPT_ACCESS:
enable = HWBRK_ACC; enable = HWBRK_ACC;
break; break;
default: default:
LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
} }
comparator_list[wp_num].used = true; comparator_list[wp_num].used = true;

122
src/target/target.c
View File

@@ -3561,20 +3561,20 @@ COMMAND_HANDLER(handle_mw_command)
struct target *target = get_current_target(CMD_CTX); struct target *target = get_current_target(CMD_CTX);
unsigned int wordsize; unsigned int wordsize;
switch (CMD_NAME[2]) { switch (CMD_NAME[2]) {
case 'd': case 'd':
wordsize = 8; wordsize = 8;
break; break;
case 'w': case 'w':
wordsize = 4; wordsize = 4;
break; break;
case 'h': case 'h':
wordsize = 2; wordsize = 2;
break; break;
case 'b': case 'b':
wordsize = 1; wordsize = 1;
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
return target_fill_mem(target, address, fn, wordsize, value, count); return target_fill_mem(target, address, fn, wordsize, value, count);
@@ -3996,39 +3996,39 @@ COMMAND_HANDLER(handle_bp_command)
int hw = BKPT_SOFT; int hw = BKPT_SOFT;
switch (CMD_ARGC) { switch (CMD_ARGC) {
case 0: case 0:
return handle_bp_command_list(CMD); return handle_bp_command_list(CMD);
case 2: case 2:
asid = 0; asid = 0;
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr); COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
return handle_bp_command_set(CMD, addr, asid, length, hw); return handle_bp_command_set(CMD, addr, asid, length, hw);
case 3: case 3:
if (strcmp(CMD_ARGV[2], "hw") == 0) { if (strcmp(CMD_ARGV[2], "hw") == 0) {
hw = BKPT_HARD;
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
asid = 0;
return handle_bp_command_set(CMD, addr, asid, length, hw);
} else if (strcmp(CMD_ARGV[2], "hw_ctx") == 0) {
hw = BKPT_HARD;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], asid);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
addr = 0;
return handle_bp_command_set(CMD, addr, asid, length, hw);
}
/* fallthrough */
case 4:
hw = BKPT_HARD; hw = BKPT_HARD;
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr); COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], asid); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], length); asid = 0;
return handle_bp_command_set(CMD, addr, asid, length, hw); return handle_bp_command_set(CMD, addr, asid, length, hw);
} else if (strcmp(CMD_ARGV[2], "hw_ctx") == 0) {
hw = BKPT_HARD;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], asid);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
addr = 0;
return handle_bp_command_set(CMD, addr, asid, length, hw);
}
/* fallthrough */
case 4:
hw = BKPT_HARD;
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], asid);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], length);
return handle_bp_command_set(CMD, addr, asid, length, hw);
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
} }
@@ -6785,25 +6785,25 @@ static int target_register_user_commands(struct command_context *cmd_ctx)
const char *target_debug_reason_str(enum target_debug_reason reason) const char *target_debug_reason_str(enum target_debug_reason reason)
{ {
switch (reason) { switch (reason) {
case DBG_REASON_DBGRQ: case DBG_REASON_DBGRQ:
return "DBGRQ"; return "DBGRQ";
case DBG_REASON_BREAKPOINT: case DBG_REASON_BREAKPOINT:
return "BREAKPOINT"; return "BREAKPOINT";
case DBG_REASON_WATCHPOINT: case DBG_REASON_WATCHPOINT:
return "WATCHPOINT"; return "WATCHPOINT";
case DBG_REASON_WPTANDBKPT: case DBG_REASON_WPTANDBKPT:
return "WPTANDBKPT"; return "WPTANDBKPT";
case DBG_REASON_SINGLESTEP: case DBG_REASON_SINGLESTEP:
return "SINGLESTEP"; return "SINGLESTEP";
case DBG_REASON_NOTHALTED: case DBG_REASON_NOTHALTED:
return "NOTHALTED"; return "NOTHALTED";
case DBG_REASON_EXIT: case DBG_REASON_EXIT:
return "EXIT"; return "EXIT";
case DBG_REASON_EXC_CATCH: case DBG_REASON_EXC_CATCH:
return "EXC_CATCH"; return "EXC_CATCH";
case DBG_REASON_UNDEFINED: case DBG_REASON_UNDEFINED:
return "UNDEFINED"; return "UNDEFINED";
default: default:
return "UNKNOWN!"; return "UNKNOWN!";
} }
} }

52
src/target/target_request.c
View File

@@ -74,15 +74,15 @@ static int target_hexmsg(struct target *target, int size, uint32_t length)
line_len = 0; line_len = 0;
for (i = 0; i < length; i++) { for (i = 0; i < length; i++) {
switch (size) { switch (size) {
case 4: case 4:
line_len += snprintf(line + line_len, 128 - line_len, "%8.8" PRIx32 " ", le_to_h_u32(data + (4*i))); line_len += snprintf(line + line_len, 128 - line_len, "%8.8" PRIx32 " ", le_to_h_u32(data + (4 * i)));
break; break;
case 2: case 2:
line_len += snprintf(line + line_len, 128 - line_len, "%4.4x ", le_to_h_u16(data + (2*i))); line_len += snprintf(line + line_len, 128 - line_len, "%4.4x ", le_to_h_u16(data + (2 * i)));
break; break;
case 1: case 1:
line_len += snprintf(line + line_len, 128 - line_len, "%2.2x ", data[i]); line_len += snprintf(line + line_len, 128 - line_len, "%2.2x ", data[i]);
break; break;
} }
if ((i%8 == 7) || (i == length - 1)) { if ((i%8 == 7) || (i == length - 1)) {
@@ -120,24 +120,24 @@ int target_request(struct target *target, uint32_t request)
} }
switch (target_req_cmd) { switch (target_req_cmd) {
case TARGET_REQ_TRACEMSG: case TARGET_REQ_TRACEMSG:
trace_point(target, (request & 0xffffff00) >> 8); trace_point(target, (request & 0xffffff00) >> 8);
break; break;
case TARGET_REQ_DEBUGMSG: case TARGET_REQ_DEBUGMSG:
if (((request & 0xff00) >> 8) == 0) if (((request & 0xff00) >> 8) == 0)
target_asciimsg(target, (request & 0xffff0000) >> 16); target_asciimsg(target, (request & 0xffff0000) >> 16);
else else
target_hexmsg(target, (request & 0xff00) >> 8, (request & 0xffff0000) >> 16); target_hexmsg(target, (request & 0xff00) >> 8, (request & 0xffff0000) >> 16);
break; break;
case TARGET_REQ_DEBUGCHAR: case TARGET_REQ_DEBUGCHAR:
target_charmsg(target, (request & 0x00ff0000) >> 16); target_charmsg(target, (request & 0x00ff0000) >> 16);
break; break;
/* case TARGET_REQ_SEMIHOSTING: /* case TARGET_REQ_SEMIHOSTING:
* break; * break;
*/ */
default: default:
LOG_ERROR("unknown target request: %2.2x", target_req_cmd); LOG_ERROR("unknown target request: %2.2x", target_req_cmd);
break; break;
} }
return ERROR_OK; return ERROR_OK;

262
src/target/x86_32_common.c
View File

@@ -331,27 +331,27 @@ static int read_mem(struct target *t, uint32_t size,
} }
switch (size) { switch (size) {
case BYTE: case BYTE:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, MEMRDB32); retval = x86_32->submit_instruction(t, MEMRDB32);
else else
retval = x86_32->submit_instruction(t, MEMRDB16); retval = x86_32->submit_instruction(t, MEMRDB16);
break; break;
case WORD: case WORD:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, MEMRDH32); retval = x86_32->submit_instruction(t, MEMRDH32);
else else
retval = x86_32->submit_instruction(t, MEMRDH16); retval = x86_32->submit_instruction(t, MEMRDH16);
break; break;
case DWORD: case DWORD:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, MEMRDW32); retval = x86_32->submit_instruction(t, MEMRDW32);
else else
retval = x86_32->submit_instruction(t, MEMRDW16); retval = x86_32->submit_instruction(t, MEMRDW16);
break; break;
default: default:
LOG_ERROR("%s invalid read mem size", __func__); LOG_ERROR("%s invalid read mem size", __func__);
break; break;
} }
if (retval != ERROR_OK) if (retval != ERROR_OK)
@@ -407,27 +407,27 @@ static int write_mem(struct target *t, uint32_t size,
return retval; return retval;
} }
switch (size) { switch (size) {
case BYTE: case BYTE:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, MEMWRB32); retval = x86_32->submit_instruction(t, MEMWRB32);
else else
retval = x86_32->submit_instruction(t, MEMWRB16); retval = x86_32->submit_instruction(t, MEMWRB16);
break; break;
case WORD: case WORD:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, MEMWRH32); retval = x86_32->submit_instruction(t, MEMWRH32);
else else
retval = x86_32->submit_instruction(t, MEMWRH16); retval = x86_32->submit_instruction(t, MEMWRH16);
break; break;
case DWORD: case DWORD:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, MEMWRW32); retval = x86_32->submit_instruction(t, MEMWRW32);
else else
retval = x86_32->submit_instruction(t, MEMWRW16); retval = x86_32->submit_instruction(t, MEMWRW16);
break; break;
default: default:
LOG_ERROR("%s invalid write mem size", __func__); LOG_ERROR("%s invalid write mem size", __func__);
return ERROR_FAIL; return ERROR_FAIL;
} }
if (retval != ERROR_OK) if (retval != ERROR_OK)
@@ -706,27 +706,27 @@ static int x86_32_common_read_io(struct target *t, uint32_t addr,
pg_disabled = true; pg_disabled = true;
} }
switch (size) { switch (size) {
case BYTE: case BYTE:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, IORDB32); retval = x86_32->submit_instruction(t, IORDB32);
else else
retval = x86_32->submit_instruction(t, IORDB16); retval = x86_32->submit_instruction(t, IORDB16);
break; break;
case WORD: case WORD:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, IORDH32); retval = x86_32->submit_instruction(t, IORDH32);
else else
retval = x86_32->submit_instruction(t, IORDH16); retval = x86_32->submit_instruction(t, IORDH16);
break; break;
case DWORD: case DWORD:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, IORDW32); retval = x86_32->submit_instruction(t, IORDW32);
else else
retval = x86_32->submit_instruction(t, IORDW16); retval = x86_32->submit_instruction(t, IORDW16);
break; break;
default: default:
LOG_ERROR("%s invalid read io size", __func__); LOG_ERROR("%s invalid read io size", __func__);
return ERROR_FAIL; return ERROR_FAIL;
} }
/* restore CR0.PG bit if needed */ /* restore CR0.PG bit if needed */
@@ -795,27 +795,27 @@ int x86_32_common_write_io(struct target *t, uint32_t addr,
pg_disabled = true; pg_disabled = true;
} }
switch (size) { switch (size) {
case BYTE: case BYTE:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, IOWRB32); retval = x86_32->submit_instruction(t, IOWRB32);
else else
retval = x86_32->submit_instruction(t, IOWRB16); retval = x86_32->submit_instruction(t, IOWRB16);
break; break;
case WORD: case WORD:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, IOWRH32); retval = x86_32->submit_instruction(t, IOWRH32);
else else
retval = x86_32->submit_instruction(t, IOWRH16); retval = x86_32->submit_instruction(t, IOWRH16);
break; break;
case DWORD: case DWORD:
if (use32) if (use32)
retval = x86_32->submit_instruction(t, IOWRW32); retval = x86_32->submit_instruction(t, IOWRW32);
else else
retval = x86_32->submit_instruction(t, IOWRW16); retval = x86_32->submit_instruction(t, IOWRW16);
break; break;
default: default:
LOG_ERROR("%s invalid write io size", __func__); LOG_ERROR("%s invalid write io size", __func__);
return ERROR_FAIL; return ERROR_FAIL;
} }
/* restore CR0.PG bit if needed */ /* restore CR0.PG bit if needed */
@@ -899,29 +899,29 @@ static int set_debug_regs(struct target *t, uint32_t address,
} }
switch (bp_type) { switch (bp_type) {
case 0: case 0:
/* 00 - only on instruction execution */ /* 00 - only on instruction execution */
DR7_SET_EXE(dr7, bp_num); DR7_SET_EXE(dr7, bp_num);
DR7_SET_LENGTH(dr7, bp_num, bp_length); DR7_SET_LENGTH(dr7, bp_num, bp_length);
break; break;
case 1: case 1:
/* 01 - only on data writes */ /* 01 - only on data writes */
DR7_SET_WRITE(dr7, bp_num); DR7_SET_WRITE(dr7, bp_num);
DR7_SET_LENGTH(dr7, bp_num, bp_length); DR7_SET_LENGTH(dr7, bp_num, bp_length);
break; break;
case 2: case 2:
/* 10 UNSUPPORTED - an I/O read and I/O write */ /* 10 UNSUPPORTED - an I/O read and I/O write */
LOG_ERROR("%s unsupported feature bp_type=%d", __func__, bp_type); LOG_ERROR("%s unsupported feature bp_type=%d", __func__, bp_type);
return ERROR_FAIL; return ERROR_FAIL;
break; break;
case 3: case 3:
/* on data read or data write */ /* on data read or data write */
DR7_SET_ACCESS(dr7, bp_num); DR7_SET_ACCESS(dr7, bp_num);
DR7_SET_LENGTH(dr7, bp_num, bp_length); DR7_SET_LENGTH(dr7, bp_num, bp_length);
break; break;
default: default:
LOG_ERROR("%s invalid request [only 0-3] bp_type=%d", __func__, bp_type); LOG_ERROR("%s invalid request [only 0-3] bp_type=%d", __func__, bp_type);
return ERROR_FAIL; return ERROR_FAIL;
} }
/* update regs in the reg cache ready to be written to hardware /* update regs in the reg cache ready to be written to hardware
@@ -1206,19 +1206,19 @@ static int set_watchpoint(struct target *t, struct watchpoint *wp)
} }
switch (wp->rw) { switch (wp->rw) {
case WPT_WRITE: case WPT_WRITE:
if (set_debug_regs(t, wp->address, wp_num, if (set_debug_regs(t, wp->address, wp_num,
DR7_BP_WRITE, wp->length) != ERROR_OK) DR7_BP_WRITE, wp->length) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
break; break;
case WPT_ACCESS: case WPT_ACCESS:
if (set_debug_regs(t, wp->address, wp_num, DR7_BP_READWRITE, if (set_debug_regs(t, wp->address, wp_num, DR7_BP_READWRITE,
wp->length) != ERROR_OK) wp->length) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
break; break;
default: default:
LOG_ERROR("%s only 'access' or 'write' watchpoints are supported", __func__); LOG_ERROR("%s only 'access' or 'write' watchpoints are supported", __func__);
break; break;
} }
watchpoint_set(wp, wp_num); watchpoint_set(wp, wp_num);
debug_reg_list[wp_num].used = 1; debug_reg_list[wp_num].used = 1;
@@ -1458,17 +1458,17 @@ COMMAND_HANDLER(handle_iow_command)
unsigned int wordsize; unsigned int wordsize;
switch (CMD_NAME[2]) { switch (CMD_NAME[2]) {
case 'w': case 'w':
wordsize = 4; wordsize = 4;
break; break;
case 'h': case 'h':
wordsize = 2; wordsize = 2;
break; break;
case 'b': case 'b':
wordsize = 1; wordsize = 1;
break; break;
default: default:
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
return target_fill_io(target, address, wordsize, value); return target_fill_io(target, address, wordsize, value);
} }

345
src/target/xscale.c
View File

@@ -517,24 +517,24 @@ static int xscale_send(struct target *target, const uint8_t *buffer, int count,
uint32_t t; uint32_t t;
switch (size) { switch (size) {
case 4: case 4:
if (endianness == TARGET_LITTLE_ENDIAN) if (endianness == TARGET_LITTLE_ENDIAN)
t = le_to_h_u32(buffer); t = le_to_h_u32(buffer);
else else
t = be_to_h_u32(buffer); t = be_to_h_u32(buffer);
break; break;
case 2: case 2:
if (endianness == TARGET_LITTLE_ENDIAN) if (endianness == TARGET_LITTLE_ENDIAN)
t = le_to_h_u16(buffer); t = le_to_h_u16(buffer);
else else
t = be_to_h_u16(buffer); t = be_to_h_u16(buffer);
break; break;
case 1: case 1:
t = buffer[0]; t = buffer[0];
break; break;
default: default:
LOG_ERROR("BUG: size neither 4, 2 nor 1"); LOG_ERROR("BUG: size neither 4, 2 nor 1");
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
buf_set_u32(t1, 0, 32, t); buf_set_u32(t1, 0, 32, t);
@@ -916,46 +916,46 @@ static int xscale_debug_entry(struct target *target)
pc = buf_get_u32(arm->pc->value, 0, 32); pc = buf_get_u32(arm->pc->value, 0, 32);
switch (moe) { switch (moe) {
case 0x0: /* Processor reset */ case 0x0: /* Processor reset */
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET; xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
pc -= 4; pc -= 4;
break; break;
case 0x1: /* Instruction breakpoint hit */ case 0x1: /* Instruction breakpoint hit */
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4; pc -= 4;
break; break;
case 0x2: /* Data breakpoint hit */ case 0x2: /* Data breakpoint hit */
target->debug_reason = DBG_REASON_WATCHPOINT; target->debug_reason = DBG_REASON_WATCHPOINT;
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4; pc -= 4;
break; break;
case 0x3: /* BKPT instruction executed */ case 0x3: /* BKPT instruction executed */
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4; pc -= 4;
break; break;
case 0x4: /* Ext. debug event */ case 0x4: /* Ext. debug event */
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4; pc -= 4;
break; break;
case 0x5: /* Vector trap occurred */ case 0x5: /* Vector trap occurred */
target->debug_reason = DBG_REASON_BREAKPOINT; target->debug_reason = DBG_REASON_BREAKPOINT;
xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
pc -= 4; pc -= 4;
break; break;
case 0x6: /* Trace buffer full break */ case 0x6: /* Trace buffer full break */
target->debug_reason = DBG_REASON_DBGRQ; target->debug_reason = DBG_REASON_DBGRQ;
xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL; xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
pc -= 4; pc -= 4;
break; break;
case 0x7: /* Reserved (may flag Hot-Debug support) */ case 0x7: /* Reserved (may flag Hot-Debug support) */
default: default:
LOG_ERROR("Method of Entry is 'Reserved'"); LOG_ERROR("Method of Entry is 'Reserved'");
exit(-1); exit(-1);
break; break;
} }
/* apply PC fixup */ /* apply PC fixup */
@@ -1815,20 +1815,20 @@ static int xscale_read_memory(struct target *target, target_addr_t address,
/* extract data from host-endian buffer into byte stream */ /* extract data from host-endian buffer into byte stream */
for (i = 0; i < count; i++) { for (i = 0; i < count; i++) {
switch (size) { switch (size) {
case 4: case 4:
target_buffer_set_u32(target, buffer, buf32[i]); target_buffer_set_u32(target, buffer, buf32[i]);
buffer += 4; buffer += 4;
break; break;
case 2: case 2:
target_buffer_set_u16(target, buffer, buf32[i] & 0xffff); target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
buffer += 2; buffer += 2;
break; break;
case 1: case 1:
*buffer++ = buf32[i] & 0xff; *buffer++ = buf32[i] & 0xff;
break; break;
default: default:
LOG_ERROR("invalid read size"); LOG_ERROR("invalid read size");
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
} }
@@ -1907,24 +1907,24 @@ static int xscale_write_memory(struct target *target, target_addr_t address,
#if 0 #if 0
for (i = 0; i < count; i++) { for (i = 0; i < count; i++) {
switch (size) { switch (size) {
case 4: case 4:
value = target_buffer_get_u32(target, buffer); value = target_buffer_get_u32(target, buffer);
xscale_send_u32(target, value); xscale_send_u32(target, value);
buffer += 4; buffer += 4;
break; break;
case 2: case 2:
value = target_buffer_get_u16(target, buffer); value = target_buffer_get_u16(target, buffer);
xscale_send_u32(target, value); xscale_send_u32(target, value);
buffer += 2; buffer += 2;
break; break;
case 1: case 1:
value = *buffer; value = *buffer;
xscale_send_u32(target, value); xscale_send_u32(target, value);
buffer += 1; buffer += 1;
break; break;
default: default:
LOG_ERROR("should never get here"); LOG_ERROR("should never get here");
exit(-1); exit(-1);
} }
} }
#endif #endif
@@ -2234,17 +2234,17 @@ static int xscale_set_watchpoint(struct target *target,
} }
switch (watchpoint->rw) { switch (watchpoint->rw) {
case WPT_READ: case WPT_READ:
enable = 0x3; enable = 0x3;
break; break;
case WPT_ACCESS: case WPT_ACCESS:
enable = 0x2; enable = 0x2;
break; break;
case WPT_WRITE: case WPT_WRITE:
enable = 0x1; enable = 0x1;
break; break;
default: default:
LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
} }
/* For watchpoint across more than one word, both DBR registers must /* For watchpoint across more than one word, both DBR registers must
@@ -2685,61 +2685,60 @@ static int xscale_analyze_trace(struct target *target, struct command_invocation
continue; continue;
switch (trace_msg_type) { switch (trace_msg_type) {
case 0: /* Exceptions */ case 0: /* Exceptions */
case 1: case 1:
case 2: case 2:
case 3: case 3:
case 4: case 4:
case 5: case 5:
case 6: case 6:
case 7: case 7:
exception = (trace_data->entries[i].data & 0x70) >> 4; exception = (trace_data->entries[i].data & 0x70) >> 4;
/* FIXME: vector table may be at ffff0000 */ /* FIXME: vector table may be at ffff0000 */
branch_target = (trace_data->entries[i].data & 0xf0) >> 2; branch_target = (trace_data->entries[i].data & 0xf0) >> 2;
break; break;
case 8: /* Direct Branch */ case 8: /* Direct Branch */
break; break;
case 9: /* Indirect Branch */ case 9: /* Indirect Branch */
xscale_branch_address(trace_data, i, &branch_target); xscale_branch_address(trace_data, i, &branch_target);
break; break;
case 13: /* Checkpointed Indirect Branch */ case 13: /* Checkpointed Indirect Branch */
xscale_branch_address(trace_data, i, &branch_target); xscale_branch_address(trace_data, i, &branch_target);
if (trace_data->num_checkpoints == 2 && chkpt == 0) if (trace_data->num_checkpoints == 2 && chkpt == 0)
chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is
*oldest */ *oldest */
else else
chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and
*newest */ *newest */
chkpt++; chkpt++;
break; break;
case 12: /* Checkpointed Direct Branch */ case 12: /* Checkpointed Direct Branch */
if (trace_data->num_checkpoints == 2 && chkpt == 0) if (trace_data->num_checkpoints == 2 && chkpt == 0)
chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is
*oldest */ *oldest */
else else
chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and
*newest */ *newest */
/* if no current_pc, checkpoint will be starting point */ /* if no current_pc, checkpoint will be starting point */
if (current_pc == 0) if (current_pc == 0)
branch_target = chkpt_reg; branch_target = chkpt_reg;
chkpt++; chkpt++;
break; break;
case 15:/* Roll-over */ case 15:/* Roll-over */
break; break;
default:/* Reserved */
LOG_WARNING("trace is suspect: invalid trace message byte");
continue;
default:/* Reserved */
LOG_WARNING("trace is suspect: invalid trace message byte");
continue;
} }
/* If we don't have the current_pc yet, but we did get the branch target /* If we don't have the current_pc yet, but we did get the branch target
@@ -3520,33 +3519,33 @@ COMMAND_HANDLER(xscale_handle_cp15)
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no);
/*translate from xscale cp15 register no to openocd register*/ /*translate from xscale cp15 register no to openocd register*/
switch (reg_no) { switch (reg_no) {
case 0: case 0:
reg_no = XSCALE_MAINID; reg_no = XSCALE_MAINID;
break; break;
case 1: case 1:
reg_no = XSCALE_CTRL; reg_no = XSCALE_CTRL;
break; break;
case 2: case 2:
reg_no = XSCALE_TTB; reg_no = XSCALE_TTB;
break; break;
case 3: case 3:
reg_no = XSCALE_DAC; reg_no = XSCALE_DAC;
break; break;
case 5: case 5:
reg_no = XSCALE_FSR; reg_no = XSCALE_FSR;
break; break;
case 6: case 6:
reg_no = XSCALE_FAR; reg_no = XSCALE_FAR;
break; break;
case 13: case 13:
reg_no = XSCALE_PID; reg_no = XSCALE_PID;
break; break;
case 15: case 15:
reg_no = XSCALE_CPACCESS; reg_no = XSCALE_CPACCESS;
break; break;
default: default:
command_print(CMD, "invalid register number"); command_print(CMD, "invalid register number");
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
reg = &xscale->reg_cache->reg_list[reg_no]; reg = &xscale->reg_cache->reg_list[reg_no];