Rewrite the function command_print() without using any specific
API from jimtcl for string manipulation.
Change-Id: I1adddd493b43e30ead26e96da09a4ee8c0a41307
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9076
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Tested-by: jenkins
The current code for cortex_a watchpoint sets the field DBGWCR:LSC
to '3', that corresponds to 'access' watchpoint.
Thus, any 'r' or 'w' watchpoint is considered to 'a'.
Convert the enum watchpoint_rw to the corresponding values for the
field DBGWCR:LSC.
Change-Id: Iccfddb3e34f3f26927983f3b00d9d5f81b06eb21
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9291
Tested-by: jenkins
aarch64_resume() set the last_run_control_op on the current core
only and left last_run_control_op as is on the rest of the SMP group.
It caused semihosting call on other cores to stop because
last_run_control_op sticked on ARMV8_RUNCONTROL_STEP
Set last_run_control_op to ARMV8_RUNCONTROL_RESUME on all cores
in the SMP group.
Change-Id: I55a97bb1f7ea25bfc5937c3cc846532cdf390064
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9247
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Semihosting worked only on the first/gdb assigned core of a SMP group.
If a semihosting call was issued on another core, aarch64_update_halt_gdb()
emitted 'halted' event on core0 before semihosting decoding started.
Use target's smp_halt_event_postponed flag to keep events from emitting
until semihosting is decoded. If a semihosting call is confirmed,
clear flags and do not send 'halted' event for any core of SMP group.
Change-Id: Ie7eff7e493c2a4df3039f49fce1744d996050a59
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9246
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
update_halt_gdb() called aarch64_poll() recursively with temporary
switching target's smp flag off to prevent deeper recursion.
This was not possible for gdb assigned target or hwthread failed
with "SMP node change, disconnect GDB from core/thread".
Therefore the aarch64_poll(gdb_target) resulted in the useless
recursion back to update_halt_gdb().
Introduce aarch64_poll_smp() with smp parameter to avoid
update_halt_gdb() recursion properly and without fiddling
with target's smp flags.
While on it, add 'aarch64_' prefix to update_halt_gdb() function.
Change-Id: I645166f50c106f4a6d4d35dc70ad49041d2442aa
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9245
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Allow memory access as soon as debug_ap is initiated.
This resolves chicken - egg problem in cortex_m_examine():
examined flag had to be set at the start of examination
to allow memory access during examination.
hla_target has memory ready to access as soon as the adapter
is initialized so we can simply return true.
Change-Id: I30b8bcb8c43775ebbd8e677da09189781bebb4ab
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9179
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Use the new test in target memory access functions
instead of target_was_examined()
Drop the test from target_read/write_u8/16/32/64() helpers
as they directly call a memory access function which does
the test again.
Change-Id: Ic1753e461d2a4b91ce3a3e1bf3e86eb2be743d46
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9178
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
GDB uses this mark when creating a dummy frame for
manual call of a function by GDB command.
With the original setting of all registers as caller_save = true
GDB inferior call fails in EL2H mode with the message
Could not fetch register "ELR_EL3"; remote failure reply '0E'
It also fails similarly in EL0 and EL1 modes.
A standard function should not change EL banked registers anyway.
Avoid marking ELx banked registers as save-restore.
Treat pauth_dmask and pauth_cmask registers similarly.
They are not typically changed in a function.
Change-Id: Ibaf32210f3fcfa9dfb15e924b888243460e85fb4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9243
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Currently, 'riscv exec_progbuf' command does not select active target.
So with multiple harts with a common debug module, program buffer may
be executed on an incorrect target.
Change-Id: Ic345b09b039c2b1e37e5b99a8534833ac2723277
Signed-off-by: Samuel Obuch <samuel.obuch@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9312
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit d7142a5727 ("target/target: Check checksum_memory
before call") added the error return if target's checksum_memory()
method is not implemented however the slow path with read buffer and
image_calculate_checksum() should be used instead.
Also the code fragment commented as /* convert to target endianness */
is a pure nonsense - it does not convert anything. Drop the conversion
loop.
Change-Id: I804605d31310698445b3ffb5e3fcad1fc43a5579
Suggested-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9242
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Tested-by: jenkins
Initial release of Flash bank driver for Bouffalo chips.
The driver currently supports BL602, BL702, BL702L series of chips.
Similar SFlash core is inside of BL808, BL606P and BL616 series,
so those might be supported in future as well.
With adapter speed set to 8000, it can reach speed 140 KiB/s.
Since chips have eXecute In Place support, and they also require
boot config in Flash at offset 0x0, it's required to have properly
crafted linker script, so OpenOCD knows where to write firmware
through gdb.
There is required flash bank parameter, which specifies the chip type.
This is required because BL702 and BL702L have same TAP ID CODE, and
there are no usable indicators to use for automatic chip type
recognition in the chip.
Change-Id: Id57336d447be3c608b39ba3ed143527bfdc0af98
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8527
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Configure reset-start event to set/clear DM resethaltreq bit.
In reset-assert event check if srst is configured.
Avoid unnecessary double reset if srst is configured.
Write dmcontrol ackhavereset in reset-deassert-post event if necessary.
Change-Id: I06b201bc5651c301912158c1436b9b3e3bc042a0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9316
Reviewed-by: Tom Hebb <tommyhebb@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The pluggable reset events are invoked only in the context of
proc ocd_process_reset_inner, so we can use $halt variable
directly and avoid proc init_reset redefinition.
Change-Id: Ie74c340c51cb2c55d8ffc9f74bb1a1a8e3461515
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9315
Tested-by: jenkins
Reviewed-by: Tom Hebb <tommyhebb@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The GD32VF103 has a perculiar reset procedure that does not fully comply
with the RISC-V Debug Specification.
Move the workaroung to the `deassert-reset-post` handler.
Change-Id: I153c866a5b7e2dff2552cc92772ce6ed77ad606b
Signed-off-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9314
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
The arithmetic addition of the returned error codes was used
as a lazy man's logical or.
Handle error passing properly.
Change-Id: I05f6d575dd7acb49cc3b3ca20b0e0b1f37d77ffe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9269
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
When not having access to the usb devices, but using the xds110, the
issue is that one first has to spend time to find the problem. The
additional error message helps others at finding this issue faster.
Solution:
"xds110.c:378 usb_connect(): libusb_open(): LIBUSB_ERROR_ACCESS"
Change-Id: Ic59e29d4dd06868920c2b912e4c866d4f176a563
Signed-off-by: Lucien Dufour <lucien.buchmann@dufour.aero>
Reviewed-on: https://review.openocd.org/c/openocd/+/9265
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
stm32f334k8 only has 12kbytes of SRAM and
flashing with the default WORKAREA of 16kbytes
will fail for images > 12k.
Change-Id: If9be0b0e7cd6e4ba15a130d8e06c74e4a0e22a61
Signed-off-by: Maximilian Schneider <max@schneidersoft.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/9283
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
With 'proc find' able to handle the replacement of '_' to '-',
drop the now unnecessary hardcoded renames.
Change-Id: I67fe3b5de8bad7611b2229fed8d2eefee848eb81
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9279
Tested-by: jenkins
Reviewed-by: Nishanth Menon <nm@ti.com>
The renaming of boards and targets is often requiring the simple
replacement of '_' with '-'.
To avoid listing such replacements in 'tcl/file_renaming.cfg', add
the automatic check in 'proc find' allowing till two replacements
of '_' with '-'.
Change-Id: I2623ea78d9c61d86189afcae2553c2910bda8389
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9278
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Replace "_" file separator with "-" file separator as recommended by
coding standards guidelines. While doing this, add the files that were
present in previous v0.12.0 release to file_renaming.cfg for this
non-trivial rename.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I88685f08f4a0cc580fa3b03f6db0d85061d65b94
Reviewed-on: https://review.openocd.org/c/openocd/+/9236
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Rename the _swd_native.cfg files as -self-hosted.cfg files as a better
representation of what we are using the configuration files to be.
Change-Id: I4eb469a219b83de6a9e7a8dfef5607306f59a7cd
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9206
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
As part of the cfg file cleanups, let us move the TI evms, launchpads
and other development platform configuration files to board/ti folder.
While at this, drop the "ti_" prefix as the folder structure gives us
the details anyways.
Change-Id: I929b88e0cf6527f3181820ad0b9b4744185eabaf
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9205
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Move the BeagleBoard.org Foundation boards to it's own folder. This
allows additional support such as BeagleV-Fire and other non TI SoC
vendor support to be subsequently added.
While doing this,
* Use "-" as separator for the file names as recommended
by coding standards.
* To maintain compatibility, add the non-trivial renames to
file_renaming.cfg
Change-Id: Ie916c9bf81fc3922bf19ed9ed2db841549d29ca9
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9204
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Move the ti targets to a TI folder. Since the folder is ti, we can
drop the "ti" prefix from the files themselves.
Done via the following script:
mkdir target/ti
FILES=`ls target/ti*.cfg target/omap*.cfg target/am335x.cfg
target/amdm37x.cfg target/icepick.cfg target/stellaris.cfg
target/davinci.cfg`
for cname in $FILES
do
bname=`basename $cname`
nname=`echo $bname|sed -e "s/^ti-//g"|sed -e "s/ti_//g"`
npath="target/ti/$nname"
echo "$cname => $npath"
fref=`git grep $cname .|cut -d ':' -f1|sort -u`
sed -i -e "s&$cname&$npath&g" $fref
git mv $cname $npath
done
Change-Id: I9f94dc6bb01f73721d4ff96be92cb51de2cbf0e2
Suggested-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9203
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For stm32l4, stm32wbx, stm32wlx the target tcl scripts try to change the
MSI oscillator's speed to 24 MHz before boosting the interface
frequency, but don't clear the RCC_CR_MSIRANGE field correctly before.
This causes the register write access to fail and leaves the clock
frequency unchanged. For the stm32wlx, the script also neglects to set
the MSIRGSEL bit, such that the frequency setting is not actually
applied.
The issue appears to not cause a problem when using an ST-Link adapter.
When using an FT4232HP, communication to the target fails after the
reset-init event, possibly because this adapter actually supports the
higher interface frequency.
This commit fixes the register accesses to make sure the RCC_CR_MSIRANGE
is cleared to zero before OR-ing the new value. For the stm32wlx, also
set the MSIRGSEL bit. Just to be safe, also fix the write access to the
FLASH_ACR_LATENCY field to clear it before OR-ing, even though it should
be zero at reset anyways.
Change-Id: Ie8320fa6ee2086981c0b1f3c18f51e171709078d
Signed-off-by: Niklas Gürtler <profclonk@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9282
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
These changes bring over some lines from the independently-developed
gd32vf103.cfg that I contributed[1] to the riscv-openocd fork of
OpenOCD. They're all minor, so I'm squashing them into one review. The
changes are as follows:
- Add boundary scan TAP.
- Mention inconsistency of CPU ID between vendor SDK and real hardware.
- Specify that there's no MMU so we don't look for one at runtime.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Change-Id: Ie8033eff436d6dbdc3eab156769a8908ccb547f6
Reviewed-on: https://review.openocd.org/c/openocd/+/6959
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The esirisc_trace.c uses macro BIT_MASK(), same name as a macro
from helper/bits.h
Drop the macro definition and use GENMASK() instead.
Change-Id: I0cc6a58e5aff3f48fa9a79a99bd28124f334c4e2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9168
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Use command_print() in order to provide an error message to the caller.
While at it, fix the return values.
Change-Id: I0f8d3466ab2729d8cca6cf4c1cff51d67982c373
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/9267
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
By reorganizing the free() of the service and its subfields, the
patch reported in 'fixes' exposes a new double free().
Issue detected by 'scan-build'.
Fix it.
Fixes: 5ff384be08 ("semihosting: fix memory leak and double free")
Change-Id: Ief4262e98c9ecdca39d4e2d77e7a0ea87cfa198c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9266
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
cJTAG OSCAN1, in lieu of 4-wire JTAG, is starting to be a configuration
option for some SiFive hardware. An FTDI-based adapter that can be
configured to drive the bidirectional pin TMSC is assumed for this
topology. Specifically, the Olimex ARM-USB-TINY-H with the ARM-JTAG-SWD
adapter, connected to a SiFive cJTAG-enabled target board is the only
known concrete topology, currently. But in theory, other FTDI based
devices that can drive a two-wire bidirectional signaling pattern could
be made to work in this scheme in the future.
These code changes are offered as a way to drive that topology. It's
translating IR/DR and JTAG traversal commands to the two-wire clocking
and signaling.
See:
- https://github.com/riscv-collab/riscv-openocd/pull/320
- https://github.com/riscv-collab/riscv-openocd/pull/736
Signed-off-by: Greg Savin <greg.savin@sifive.com>
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Change-Id: Ia1daa2c01227c4b0005be947b2bb0de81a800874
Reviewed-on: https://review.openocd.org/c/openocd/+/6981
Tested-by: jenkins
On Cortex-M7 only, several registers in System Control Space (SCS)
are not accessible when the CPU is under reset, generating a bus
error.
This causes OpenOCD to fail examining the CPU when the board reset
button is pressed or when the flag 'connect_assert_srst' is used
on 'reset_config' command.
Introduce a deferred identification of the cache and run it during
polling and at target halted (just in case of polling disabled).
Change-Id: Ia5c582ae95f825c5fb8c2dcfb320142f7ac04a9f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9232
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
In a SMP configuration 'resumed' event was emitted only for
the active core, in contradiction to 'halted' event, which
gets emitted for all cores from the SMP group:
> resume
target event 3 (resume-start) for core stm32mp15x.cpu0
target event 2 (resumed) for core stm32mp15x.cpu0
target event 4 (resume-end) for core stm32mp15x.cpu0
target event 7 (gdb-start) for core stm32mp15x.cpu0
> halt
target event 0 (gdb-halt) for core stm32mp15x.cpu1
target event 1 (halted) for core stm32mp15x.cpu1
target event 0 (gdb-halt) for core stm32mp15x.cpu0
target event 1 (halted) for core stm32mp15x.cpu0
target event 8 (gdb-end) for core stm32mp15x.cpu0
Emit 'resumed' event in cortex_a_restore_smp().
While on it replace adding the returned errors together
with the proper error handling.
Change-Id: I9debef0884519cde767707f78f163b136ecc7aa5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9244
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Add command to re-load option bytes.
Tested with STM32L072CZ and STM32L152RCT6.
Change-Id: I5653f2222a48af1fe0332d4bdc3552e481e375d0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8998
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Cherry-picked from [1].
To replicate the issue that this fixes:
1. Connect to a multi-hart RISC-V target configured as an SMP group.
2. Start a GDB instance against the running OpenOCD.
3. Observe that GDB might display "warning: multi-threaded target
stopped without sending a thread-id, using first non-exited thread."
4. Set a breakpoint in code that any non-hart-0 hart is expected to
reach (but hart 0 is not expected to reach).
5. Allow a non-hart-0 hart to reach the breakpoint.
6. Remove the breakpoint.
7. Do a few sequential `stepi` commands in GDB.
8. Observe that GDB displays "Switching to Thread 1" even though the
thread that was just single stepped was not Thread 1 in GDB. Also
observe that the register values in GDB correspond to the thread that
was single-stepped, not Thread 1. Basically GDB erroneously starts to
consider thread 1 to be current, when in fact the thread that was
single-stepped is still current.
The changes in this pull request are intended to avoid the erroneous
"Switching to Thread 1" described in (8) above.
What was happening was that, in a couple areas of code, non-hart-0 harts
weren't seen as belonging to an RTOS module, and this had the effect of
(1) bypassing `hwthread_update_threads()` being called after a halt; (2)
omitting a thread ID in a stop reply over GDB remote protocol connection
(requiring GDB to take an arbitrary guess of current thread id, a guess
that is wrong unless the current thread happens to be hart 0).
Link: https://github.com/riscv-collab/riscv-openocd/pull/675 [1]
Change-Id: I9872062dfa0e3f1ca531d282d52a1b04c527546a
Signed-off-by: Greg Savin <greg.savin@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9183
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit 0847a4d7fb ("jtag/commands: Use 'unsigned int' data type")
introduced bug when changing loop variable from `int` to `unsigned int`.
Instead of getting negative and terminating the loop, the value wraps
around to `INT_MAX` and the loop never finishes.
Change-Id: I055025a1f8eb4abe50955607b3e89530dfd92af4
Signed-off-by: NikLeberg <niklaus.leuenb@gmail.com>
Fixes: 0847a4d7fb ("jtag/commands: Use 'unsigned int' data type")
Reviewed-on: https://review.openocd.org/c/openocd/+/9078
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Gdb uses length 3 to set breakpoint on a 4 byte Thumb-2
instruction. Without this patch a breakpoint on down aligned word
address was set. If the requested address was not word aligned,
the breakpoint triggered at previous instruction and was not
recognised properly by gdb.
Set breakpoint on whole word if aligns with requested address,
otherwise use length 2 and set byte mask.
Change-Id: I12d1c57b7154e64abdf23dd7cd31714f9d8ec6f0
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9211
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Some targets have no means to find out which watchpoint triggered
the debug halt. Resolve properly the trivial and most used case
when only one watchpoint is set.
Change-Id: I683933ec43e6ca0fed84a08a2aa222ed8a6e277f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9210
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Resolve two problems that occurred when working with semihosting service
through multiple connection cycles (connect-disconnect-reconnect):
1) Double free:
When the same service handles multiple connections sequentially,
the same memory gets freed repeatedly, because function
'semihosting_service_connection_closed_handler()' incorrectly frees
service->priv->name on every connection closure.
2) Memory leak:
Function 'free_services()' misses service->priv->name cleanup for
semihosting redirection. Memory remains allocated after service
destruction.
The solution introduces a new 'dtor()' field in the service structure
that is called exactly once during free_service() execution.
To reproduce the issue, you can do the following:
1. openocd -f target.cfg -c init -c 'arm semihosting enable' -c
'arm semihosting_redirect tcp 4445'
# in another terminal
2. nc localhost 4445
3. Ctr+C
4. nc localhost 4445
5. Ctr+C
Change-Id: I0dc8021cc3e21c5af619c71a1821a1afe9bffe78
Signed-off-by: Kulyatskaya Alexandra <a.kulyatskaya@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9196
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
