Let the target algorithm be running in the background and buffer data
continuously through a FIFO. This reduces or removes the effect of latency
because only a very small number of queue executions needs to be done per
buffer fill. Previously, the many repeated target state changes, register
accesses (really inefficient) and algorithm uploads caused the flash
programming to be latency bound in many cases. Now it should scale better
with increased throughput.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Access the different flash banks' registers using a bank specific register
base and a register specific offset. This is equivalent but feels more
natural.
Some accesses were discovered that maybe should not be hard coded to bank0
registers. Add a note about that.
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
crc check was always performed on newly flashed data, now it is optional
flash mem can be locked by writing a specific word to a specific address in flash.
to verify flash, target must be halted, and this will (when the new halt sequence is implemented) require reseting the chip. if the target is reset after writing the lock words, then it will lock, hence the CRC will fail because it is not possible to read stuff from the target.
also added a function that resets the jtag state machine.
this is not used yet, but will be soon.
it is implemented to allow strict control over JTAG state machine, necessary to implement to halt and unlocking sequences.
There are some older atmel nor chips which have negated logic for
TopBottom detection. This patch adds a special handling for the old
chips. This is the same mechanism as implemented in linux kernel.
Signed-off-by: Andreas Bießmann <andreas.devel@gmail.com>
Issue warning when the old cmd is used and redirect to new supported one.
These deprecated cmds will be removed at some point.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Use consistent names for the stm32 family flash drivers, eg.
stm32x -> stm32f1x
stm32f2xxx -> stm32f2x
this makes it easier to add support for newer stm32 families.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Use "git revert <commit>" to revert this commit, then build and
repair and post patch to the mailing list.
Warnings generated with:
nios2-elf-gcc (GCC) 3.4.6 (Altera Nios II 9.1 b222)
openocd/src/target/dsp5680xx.c: In function 'eonce_rx_upper_data':
openocd/src/target/dsp5680xx.c:252: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'eonce_rx_lower_data':
openocd/src/target/dsp5680xx.c:268: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'eonce_pc_store':
openocd/src/target/dsp5680xx.c:508: warning: dereferencing type-punned
pointer will break strict-aliasing rules
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_read':
openocd/src/target/dsp5680xx.c:736: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c:737: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write_8':
openocd/src/target/dsp5680xx.c:823: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write':
openocd/src/target/dsp5680xx.c:938: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c:941: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_f_wr':
openocd/src/target/dsp5680xx.c:1355: warning: cast increases required
alignment of target type
there was a check in clearing the status register that
called exit() if the target was running. target_write_memory()
has such a check and will report the error correctly.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Update devices as per the latest programming manual.
We now use the full DEVID to identify the target. Previously we used
a 8bit id but that has now been changed in the manual.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
production processor versions increment, thus the version
bits should be ignored for future proofing. e.g.
Engineering sample version == 0x00, production version 0x01
Fix a bunch of typos.
Most are in code comments, so nothing should break. UNKOWN_COMMAND and
CMD_UNKOWN are not used elsewhere, so correcting the spelling should
also not break anything.
Based on the lpc3180 driver, but released as a separate driver for two reasons:
1) I don't have an lpc3180 to test it against, so it might unintentionally break compatibility.
2) It's using a different OOB layout than lpc3180.
Rewritten so that it no longer borrows code from the NXP CDL library. Instead borrowing code from the u-boot port to lpc32xx, written by Kevin Wells.
Tested on lpc3250 (Hitex LPC3250-Stick). OOB layout is compatible with LPCLinux.
ARM11 broke with aa61a3b3d8
as the code only checked for arm 7/9.
CFI probably needs work for non-ARM targets but perhaps
not adding working area memory to e.g. MIPS will give
the default slow CFI support.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
