Add support for the Real-Time CPU (RCPU) of K1, which is a 32-bit RISC-V
N308 High-Efficiency Processor Core designed by Nuclei System Technology
Co. Ltd.
The JTAG interface can be configured to connect to either X60s or RCPU
processors. To enable JTAG for RCPU, set TARGET to "rcpu".
For example:
openocd -c "set TARGET rcpu" -f interface/cmsis-dap.cfg \
-f target/spacemit-k1.cfg
Change-Id: I9cd62fac332137afac17efa52702818de8f0b6f5
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-on: https://review.openocd.org/c/openocd/+/8821
Reviewed-by: liangzhen <zhen.liang@spacemit.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add SWD multidrop setting.
Fix the name of AP #1 to AUX-AP
Set AUX-AP CSW Prot bit[0] to make RISC-V debug accessible on AUX-AP.
Change-Id: I496e07acfe90dd858e4403176a8330d8c1a0b560
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8752
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
AM261[1] is a optimized cutdown of AM263P SoC. The key difference is
the reduced number of R5F cores which is now dropped down to 2, and
the DIE ID is different from AM263p, but all other definitions are
compatible, so reuse the definition.
[1] https://www.ti.com/product/AM2612
Change-Id: Ib6ca0b59d0b8991df6e4ab349d371187438cb393
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8792
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
AM263P[1] adds additional features to AM263 SoC. [2] provides a
detailed list of differences, however, the key difference from
processor usage perspective is the increased SRAM and Remote L2(RL2)
Cache for improved performance of R5F. To differentiate the DIE ID
is different, however rest of the processor description remain
compatible to AM263, hence reuse the definition.
[1] https://www.ti.com/product/AM263P4
[2] https://www.ti.com/lit/pdf/spradb3
Change-Id: If47935caf1f995d7e606547e0d6545c39544678a
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8770
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
TI K3 Debug systems have a Power Access Port (Power-AP) which allows
for functionality such as reset via debugger that using the SPREC
register. SoCs/Boards that do not have support for SRST or TRST can
make use of this to force a system reset via debug access.
Change-Id: Ic5f9cc7f7fba77b353b0c0b42d8afc02502251a0
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8769
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
BL602, BL702 and BL702L series of chips are sharing same architecture,
so they all need same software reset mechanism as well.
Only difference (in terms of configuration needed for JTAG) are TAP ID,
workarea address and size. This is addressed by creating bl602_common.cfg
tcl file, which contains all those common stuff between the chips.
The script is prefixed by bl602, as this was
first *publicly* available chip from Bouffalo with this architecture.
This patch also improves reset mechanism. Previous reset mechanism did not
worked properly when slower JTAG adapter was used (it attached too late).
New reset mechanism uses various methods to keep CPU in BootROM, until
the JTAG adapter does not attach again after reset. Additionally,
we trigger SW Reset by directly using DMI commands to write to register
with system bus method, to avoid getting error about unsuccessful write.
The new method works on both FT232H (8MHz JTAG clock) and
unnamed CMSIS-DAP dongle (1.5MHz JTAG clock).
Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8593
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The RISC-V coprocessor is currently not supported. It is attached to the
DAP via AP#2 but the AP implementation is unknown.
The nRFL54L series uses resistive RAM (RRAM) as non-volatile memory
which can be programmed directly. Since it does not fit in the current
flash memory infrastructure of OpenOCD there is no NVM support so far.
Change-Id: I9934af4fd3bb8b7272954fc4b17638c7dabbbee0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8609
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In previous implementation, it was known that it does not perform
full reset, and that some peripherals, such as GLB core,
which handles among other stuff GPIOs, was not reset.
It was presumed, that full reset by software is not possible,
although, by accident, even when comment says that
CTRL_PWRON_RESET is set to 1, it is not
(value written into 0x40000018 supposed to be 0x7, not 0x6).
CTRL_PWRON_RESET indeed triggers full "power-on like" reset,
so this method is implemented in this commit.
There are some workarounds to make reset seamless, without any
error messages, which are described in comments of TCL script.
Only down-side of this reset is, that chip is halted after reset
bit later in BootROM than previous implementation,
but it's still good.
Change-Id: Ife2cdcc6a2d96a2e24039bfec149705baf046318
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8529
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The _targets has to be global as it is accessed at the end of this file.
This is already the case for setup_a5x {}, assure it is the same way for
setup_crx{} . Without this change, the _targets at the end of this file
is empty in case the Cortex-R is the boot core, fix this.
Change-Id: I4979e3125ec7d93bbd56eee0096ae1d9c5f6a565
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8470
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Adds initial support for the BL702 series of chips, BL702, BL704 and BL706.
No flash bank support yet.
File name bl702.tcl was chosen over bl70x.tcl, because Bouffalo Lab
uses bl702 to mark the whole series in many of their tools.
The ndmreset bit in the RISC-V Debug Module isn't implemented correctly,
so it doesn't trigger a system reset as it should.
To solve this problem, the software reset is implemented
in the reset-assert-pre hook, which uses best reset method I could find.
What is not reset is the GLB core, which handles GPIOs, pinmux, etc.
The reset mechanism has been extensively tested, and works correctly
for both "reset run" and "reset halt", which the latter
halts very early in the BootROM.
Change-Id: I5ced6eb3902d1b9d9c1bba56f817ec5dc3493cb0
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8407
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Direct memory driver swd native configuration for am62a7, am62p and
J722S SoCs. All three share common memory map for the debug address
map, so there is a strong reuse. However, introduce board file
specific to the board to allow users to directly get started.
Change-Id: I5609925a2e9918fd4c91d9fd40fbee98de27fdbc
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8283
Tested-by: jenkins
Reviewed-by: Vaishnav M A <vaishnav@beagleboard.org>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
The flag '-coreid' is used by the command 'target create' to
specify the debug controller of the target, either in case of a
single debug controller for multiple CPU (e.g. RISC-V harts) or
in case of multiple CPU on a DAP access port (e.g. Cortex-A SMP
cluster).
It is also currently used to specify the CPU ID in a SMP cluster,
but this is going to be reworked.
This flag has no effects on Cortex-M; ARM specifies that only one
CPU Cortex-M can occupy the DAP access port by using hardcoded
addresses.
The flash driver 'psoc6' uses the flag '-coreid' to detect if the
current target is the Cortex-M0 on AP#1 or the Cortex-M4 on AP#2
in the SoC.
There are other ways to run such detection, without using such
unrelated '-coreid' flag, e.g. using the AP number or the arch
type of the target.
Use the arch type to detect Cortex-M0 (ARM_ARCH_V6M) vs Cortex-M4
(ARM_ARCH_V7M).
Drop the flags '-coreid' from the psoc6 configuration file.
Change-Id: I0b9601c160dd4f2421a03ce6e3e7c55c6212f714
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8128
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Both devices can be configured with or without SWD multidrop.
nRF53 network core is examined on demand to avoid problems
when the core is forced off.
Change-Id: I08f88ff48ff7ac592e9214b89ca8e5e9428573a5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8113
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Configure the TRACECONFIG.TRACEPORTSPEED register depending on the
trace clock speed. Also catch invalid trace clock speeds.
Change-Id: I1ece1cc59da539732d2d71f296fd55799c195387
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8256
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Use 'error' instead of 'echo' for error messages. Otherwise, capturing
is always started, for example with an unsupported device.
While at it, make the error messages more consistent and clear.
Change-Id: I83c9abfb4514e6b638c4be14651e67f768af8bad
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8255
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: <post@frankplowman.com>
Add some helpers for booting ZynqMPs over JTAG. Normally, the CSU ROM
will load boot.bin from the boot medium. However, when booting from JTAG
we have to do this ourselves. There are generally two parts to this.
First, we need to load the PMU firmware. Xilinx's tools do this by
attaching to the PMU (a Microblaze CPU) over JTAG. However, the TAP is
undocumented and we don't have any microblaze support in-tree. So
instead we do it the same way FSBL does it:
- We ask the PMU to halt
- We load the firmware into the PMU RAM
- We ask the PMU to resume
The second thing we need to do is start one of the APU cores. When an
APU is released from reset, it starts executing at the value of its
RVBARADDR. While we could load the APU firmware over the AXI target,
it is faster to load it over the APU target. To do this, we put the APU
into an infinite loop before halting it. As an aside, I chose to use the
"APU" terminology as opposed to "core" to make it clear that these
commands operate on the A53 cores and not the R5F cores.
Typical usage of these commands could look something like
targets uscale.axi
boot_pmu /path/to/pmu-firmware.bin
boot_apu /path/to/u-boot-spl.bin
But of course there is always the option to call lower-level commands
individually if your boot process is more unusual.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I816940c2022ccca0fabb489aa75d682edd0f6138
Reviewed-on: https://review.openocd.org/c/openocd/+/8133
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
After 'reset run' or 'reset halt' the loaded application
is expected to manipulate RAMON register to workaround
the known silicon errata.
Moreover, writing to RAMON register from 'reset-end' event
after 'reset run' may collide with application intentions.
Use the workaround in 'reset-init' event only to ensure
correct function of target algorithms.
Change-Id: I7d2d92e6805a05a83676edb46b3163ef39b9a7e4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8104
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Use the newer driver name 'nrf5' instead.
While on it set the unused parameters of flash bank
creation to zero.
While on it remove 2 empty comments.
Change-Id: I9cf0eadc5b696e6c8b7e6aec0ea3345967523e87
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8103
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
- Example for configuring multiple non-SMP
Xtensa cores e.g. for heterogeneous debug
- JTAG only at this time; DAP out of scope
- Dual-Xtensa Palladium example via VDebug
- Update Xtensa core config examples
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I6d2b3d13fa8075416dcd383cf256a3e8582ee1c1
Reviewed-on: https://review.openocd.org/c/openocd/+/8078
Tested-by: jenkins
Reviewed-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This change implements the support for the ARM Debug Interface v6.
The DAP-level interface properly selects the DP Banks and AP address.
Sample ARM configuration DAP and JTAG scripts have been updated.
Change-Id: I7df87ef764bca587697c778810443649a7f46c2b
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8067
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
S32K General-Purpose Microcontrollers
Scalable, low-power Arm® Cortex®-M series-based microcontrollers AEC-Q100
qualified with advanced safety and security and software support for
industrial and automotive ASIL B/D applications in body, zone control,
and electrification.
Change-Id: I4143258535437c18b81802436267bfd561de9d31
Signed-off-by: David Vidrie Leon <davidvidrie@geotab.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8012
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Tested with APM32F103CBT6 using JTAG and SWD transport. All flash
operations, including sector and device protection, work as expected.
Change-Id: Ibefe1a65d710aea87b86ab7ff8a4153512a0ea4f
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8017
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested with APM32407RGT6 using JTAG and SWD transport. All flash
operations, including sector and device protection, work as expected.
Revision identifier (0x0009) is not updated due to missing documentation.
Change-Id: I33f4630fd00096656369ecc923aea2dcad77c7d3
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8016
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested with APM32F030C8T using SWD transport. All flash operations,
including sector and device protection, work as expected.
Revision identifier (0x0011) is not updated due to missing documentation.
Introduce a new directory structure that contains the manufacturer for
the sake of clarity.
Change-Id: I679387943b09fef640f8f8b6904e542f4e4b29aa
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8015
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This has a quite complex JTAG router chain requiring both a custom
BYPASS instruction to access child taps, and JTAG configuration to
enable individual DAP nodes.
Change-Id: I6f5345764e1566d70c8526a7e8ec5d250185bd2c
Signed-off-by: Henrik Nordström <henrik.nordstrom@addiva.se>
Reviewed-on: https://review.openocd.org/c/openocd/+/8042
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add support for the TI K3 family J722S SoC. This SoC is a variant of
AM62P chassis with a different JTAG ID, additional R5 added in (along
with C7x and few other peripheral changes). Reuse existing definition.
For further details, see https://www.ti.com/lit/zip/sprujb3
Change-Id: I754e6be8df3a26212437ea955f6a791d7c99b0c8
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8049
Reviewed-by: Bryan Brattlof <hello@bryanbrattlof.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
On this chip, the ndmreset bit in the RISC-V debug module doesn't
trigger a system reset like it should. To work around this, add a custom
"reset-assert" handler in its config file that resets the system by
writing to memory-mapped registers.
I've tested this workaround on a Sipeed Longan Nano dev board with a
GD32VF103CBT6 chip. It works correctly for both "reset run" and "reset
halt" (halting at pc=0 for the latter).
I originally submitted[1] this workaround to the riscv-openocd fork of
OpenOCD. That fork's maintainers accepted it, but have not upstreamed it
like they have several other of my changes.
[1] https://github.com/riscv/riscv-openocd/pull/538
Change-Id: I7482990755b300fcbe4963c9a599d599bc02684d
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6957
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Add support for the TI K3 family AM243 SoC. This SoC is built on the
same base of AM642, so reuse the configuration with the exception of
Cortex-A53 which is not available on this device.
For further details, see https://www.ti.com/lit/pdf/spruim2
Change-Id: I971ba878b0f503e5120f6853634776eb61d05080
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7946
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The AM2x family of K3 SoCs typically do not contain a Cortex-A53 or
A72 processor. So, make the cpu "up" functions available when armv8
processor count > 0.
Change-Id: I985b194fe7cc63e4134ad84ccd921cc456eb412f
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7944
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Convert the memory access ap port num as a variable to allow support
for the AM2x family of K3 SoCs.
Change-Id: Ibd96c94055721f60d95179dab21d014c15b0f562
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7943
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Convert the Cortex-R5 ap port num as a variable to allow support for
the AM2x family of K3 SoCs.
Change-Id: I7dc8b459dca8b5f21395230b5cb782b14538bd48
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7942
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
