9b21a31eb7
Historically swj_newdap was necessary to handle HLA properly.
Since commit 60f104f450 ("hla_transport: split command
registration per transport") there is no point in using
swj_newdap on SWD only devices.
Change-Id: Ib4d7eb5935e0b44087cc8ea73ab187a417413db6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9421
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
121 lines
3.7 KiB
INI
121 lines
3.7 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# RP2040 is a microcontroller with dual Cortex-M0+ core.
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# https://www.raspberrypi.com/documentation/microcontrollers/silicon.html#rp2040
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# The device requires multidrop SWD for debug.
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transport select swd
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME rp2040
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}
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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# Nonzero FLASHSIZE supresses QSPI flash size detection
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if { [info exists FLASHSIZE] } {
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set _FLASHSIZE $FLASHSIZE
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} else {
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# Detect QSPI flash size based on flash ID or SFDP
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set _FLASHSIZE 0
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x01002927
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}
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# Set to '1' to start rescue mode
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if { [info exists RESCUE] } {
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set _RESCUE $RESCUE
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} else {
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set _RESCUE 0
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}
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# Set to '0' or '1' for single core configuration, 'SMP' for -rtos hwthread
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# handling of both cores, anything else for isolated debugging of both cores
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if { [info exists USE_CORE] } {
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set _USE_CORE $USE_CORE
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} else {
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set _USE_CORE SMP
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}
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set _BOTH_CORES [expr { $_USE_CORE != 0 && $_USE_CORE != 1 }]
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swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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# The rescue debug port uses the DP CTRL/STAT bit DBGPWRUPREQ to reset the
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# PSM (power on state machine) of the RP2040 with a flag set in the
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# VREG_AND_POR_CHIP_RESET register. Once the reset is released
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# (by clearing the DBGPWRUPREQ flag), the bootrom will run, see this flag,
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# and halt. Allowing the user to load some fresh code, rather than loading
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# the potentially broken code stored in flash
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if { $_RESCUE } {
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dap create $_CHIPNAME.rescue_dap -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0xf -ignore-syspwrupack
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init
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# Clear DBGPWRUPREQ
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$_CHIPNAME.rescue_dap dpreg 0x4 0x00000000
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# Verifying CTRL/STAT is 0
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set _CTRLSTAT [$_CHIPNAME.rescue_dap dpreg 0x4]
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if {[expr {$_CTRLSTAT & 0xf0000000}]} {
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echo "Rescue failed, DP CTRL/STAT readback $_CTRLSTAT"
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} else {
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echo "Now restart OpenOCD without RESCUE flag and load code to RP2040"
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}
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shutdown
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}
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# core 0
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if { $_USE_CORE != 1 } {
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dap create $_CHIPNAME.dap0 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0
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set _TARGETNAME_0 $_CHIPNAME.core0
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target create $_TARGETNAME_0 cortex_m -dap $_CHIPNAME.dap0 -coreid 0
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# srst does not exist; use SYSRESETREQ to perform a soft reset
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$_TARGETNAME_0 cortex_m reset_config sysresetreq
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# After a rescue reset or if halted in BOOTSEL connect the flash to enable
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# reads from the XIP cached mapping area
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$_TARGETNAME_0 configure -event reset-init { rp2xxx rom_api_call CX }
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}
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# core 1
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if { $_USE_CORE != 0 } {
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dap create $_CHIPNAME.dap1 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 1
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set _TARGETNAME_1 $_CHIPNAME.core1
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target create $_TARGETNAME_1 cortex_m -dap $_CHIPNAME.dap1 -coreid 1
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$_TARGETNAME_1 cortex_m reset_config sysresetreq
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}
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if {[string compare $_USE_CORE SMP] == 0} {
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$_TARGETNAME_0 configure -rtos hwthread
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$_TARGETNAME_1 configure -rtos hwthread
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target smp $_TARGETNAME_0 $_TARGETNAME_1
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}
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if { $_USE_CORE == 1 } {
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set _FLASH_TARGET $_TARGETNAME_1
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} else {
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set _FLASH_TARGET $_TARGETNAME_0
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}
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# QSPI flash size detection during gdb connect requires to back-up RAM
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set _WKA_BACKUP [expr { $_FLASHSIZE == 0 }]
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$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup $_WKA_BACKUP
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME rp2xxx 0x10000000 $_FLASHSIZE 0 0 $_FLASH_TARGET
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if { $_BOTH_CORES } {
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# Alias to ensure gdb connecting to core 1 gets the correct memory map
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flash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME
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# Select core 0
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targets $_TARGETNAME_0
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}
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