Keep clocks running in low power modes. Stop watchdogs from interfering with the debug session. Set up PLL and increase clock at reset init. Change-Id: I232d769d893d54e4ea9411c46c56b19587b69919 Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2707 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2.3 KiB
2.3 KiB