Keep clocks running in low power modes. Stop watchdogs from interfering with the debug session. Set up PLL and increase clock at reset init. Change-Id: I984d2018f7d47a1042f1e12894563154fa7b566c Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2196 Tested-by: jenkins Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
3.4 KiB
3.4 KiB