f36ab02a80
Move the configuration files into a dedicated vendor folder as required by the developer guidelines. Change-Id: I9ed39e32b6281a9cb8510914690f3f7751b795c8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/9271 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
138 lines
4.4 KiB
INI
138 lines
4.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# GigaDevice GD32VF103 target
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#
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# https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/
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#
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source [find mem_helper.tcl]
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transport select jtag
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME gd32vf103
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}
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# The smallest RAM size 6kB (GD32VF103C4/T4/R4)
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x1800
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}
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# Example OpenOCD configurations from GigaDevice/Nuclei expect a cpu IDCODE of
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# 0x1e200a6d instead. It's unclear if any units with that IDCODE exist in the
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# wild. Please report a bug if you have such a unit.
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
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jtag newtap $_CHIPNAME bs -irlen 5 -expected-id 0x790007a3
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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# Disable virtual address translation since we don't have an MMU. Nothing will
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# break without this line, but OpenOCD will do a few unnecessary register reads
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# to figure it out on its own.
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$_TARGETNAME riscv virt2phys_mode off
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proc default_mem_access {} {
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riscv set_mem_access progbuf
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}
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default_mem_access
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
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# DBGMCU_CR register cannot be set in examine-end event as the running RISC-V CPU
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# does not allow the debugger to access memory.
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# Stop watchdogs at least before flash programming.
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$_TARGETNAME configure -event reset-init {
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# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP
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mmw 0xE0042004 0x00000300 0
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}
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set dmcontrol 0x10
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set dmcontrol_dmactive [expr {1 << 0}]
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set dmcontrol_clrresethaltreq [expr {1 << 2}]
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set dmcontrol_setresethaltreq [expr {1 << 3}]
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set dmcontrol_ackhavereset [expr {1 << 28}]
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set dmstatus 0x11
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set dmstatus_allunavail [expr {1 << 12}]
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set dmstatus_allhavereset [expr {1 << 19}]
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$_TARGETNAME configure -event reset-start {
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if {$halt} {
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set ctrl [expr {$::dmcontrol_dmactive | $::dmcontrol_setresethaltreq}]
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} else {
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set ctrl [expr {$::dmcontrol_dmactive | $::dmcontrol_clrresethaltreq}]
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}
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riscv dmi_write $::dmcontrol $ctrl
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}
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# On this chip, ndmreset (the debug module bit that triggers a software reset)
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# doesn't work. So for JTAG connections without an SRST, we need to trigger a
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# reset manually. This is an undocumented reset sequence that's used by the
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# JTAG flashing script in the vendor-supplied GD32VF103 PlatformIO plugin:
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#
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# https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2
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#
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$_TARGETNAME configure -event reset-assert {
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set reset_config_options [reset_config]
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# If hardware NRST signal is connected and configured, reset has been
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# triggered. Avoid second reset and return early
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if {[string match {srst_only *} $reset_config_options]
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|| [string match {srst_and_trst *} $reset_config_options]} {
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return
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}
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# Halt the core so that we can write to memory. We do this first so
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# that it doesn't clobber our dmcontrol configuration.
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halt
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echo "gd32vf103 reset workaround halt=$halt"
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# Unlock 0xe0042008 so that the next write triggers a reset
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mww 0xe004200c 0x4b5a6978
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# We need to trigger the reset using abstract memory access, since
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# progbuf access tries to read a status code out of a core register
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# after the write happens, which fails when the core is in reset.
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riscv set_mem_access abstract
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# Go!
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mww 0xe0042008 0x1
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# Put the memory access mode back to what it was.
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default_mem_access
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}
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# On GD32VF103 the specification's requirement that each hart is in "exactly
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# one of four states" is violated and, during reset, report harts as both
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# unavailable and halted/running. To work around this, after the havereset is
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# lowered in the main deassert_reset procedure, we wait for the absence of the
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# unavailable state.
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$_TARGETNAME configure -event reset-deassert-post {
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set timeout_ms 100
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set start [clock milliseconds]
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while {1} {
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set status [riscv dmi_read $::dmstatus]
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if {!($status & $::dmstatus_allunavail)} {
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break
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}
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if {[clock milliseconds] - $start > $timeout_ms} {
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error {Timed out waiting for the hart to become available after a reset}
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}
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}
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set ctrl [expr {$::dmcontrol_dmactive | $::dmcontrol_clrresethaltreq}]
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if {$status & $::dmstatus_allhavereset} {
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set ctrl [expr {$ctrl | $::dmcontrol_ackhavereset}]
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}
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riscv dmi_write $::dmcontrol $ctrl
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}
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