c7384117c6
This should allow to share common configs for both regular access and high-level adapters. Use the newly-added functionality in stlink and icdi drivers, amend the configs accordingly. Runtime-tested with a TI tm4c123g board. Change-Id: Ibb88266a4ca25f06f6c073e916c963f017447bad Signed-off-by: Paul Fertser <fercerpav@gmail.com> [gus@projectgus.com: context-specific deprecation warnings] Signed-off-by: Angus Gratton <gus@projectgus.com> [andrew.smirnov@gmail.com: additional nrf51.cfg mods] Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Tested-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Reviewed-on: http://openocd.zylin.com/1664 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
18 lines
634 B
INI
18 lines
634 B
INI
# NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB Local On-Chip SRAM,
|
|
set CHIPNAME lpc1788
|
|
set CPUTAPID 0x4ba00477
|
|
set CPURAMSIZE 0x10000
|
|
set CPUROMSIZE 0x80000
|
|
|
|
# After reset the chip is clocked by the ~12MHz internal RC oscillator.
|
|
# When board-specific code (reset-init handler or device firmware)
|
|
# configures another oscillator and/or PLL0, set CCLK to match; if
|
|
# you don't, then flash erase and write operations may misbehave.
|
|
# (The ROM code doing those updates cares about core clock speed...)
|
|
#
|
|
# CCLK is the core clock frequency in KHz
|
|
set CCLK 12000
|
|
|
|
#Include the main configuration file.
|
|
source [find target/lpc17xx.cfg]
|