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tcl: add config file for hpmicro devices and boards

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- add board and device config files
- add interface config file for hpmicro evk boards

Change-Id: I8afb0b734b1064d71c4af3c118c7777d0ead9e6b
Signed-off-by: Ryan QIAN <jianghao.qian@hpmicro.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8697
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Ryan QIAN
2025-01-07 15:21:02 +08:00
committed by Tomas Vanek
parent 26507adfad
commit 0e2f990c87
23 changed files with 1837 additions and 0 deletions
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66
tcl/board/hpmicro/hpm5300evk.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2023 HPMicro
adapter speed 10000
source [find interface/hpmicro/hpmicro_evk.cfg]
source [find target/hpmicro/hpm5300.cfg]
# openocd flash driver argument:
# - option0:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# [15:8] Dummy cycles
# 0 - Auto-probed / detected / default value
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
# [7:4] Misc.
# 0 - Not used
# 1 - SPI mode
# 2 - Internal loopback
# 3 - External DQS
# [3:0] Frequency option
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
# - option1:
# [31:20] Reserved
# [19:16] IO voltage
# 0 - 3V / 1 - 1.8V
# [15:12] Pin group
# 0 - 1st group / 1 - 2nd group
# [11:8] Connection selection
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
# [7:0] Drive Strength
# 0 - Default value
# xpi0 configs
# - flash driver: hpm_xpi
# - flash ctrl index: 0xF3000000
# - base address: 0x80000000
# - flash size: 0x2000000
# - flash option0: 0x5
# - flash option1: 0x1000
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3000000 0x5 0x1000
proc init_clock {} {
mww 0xF4000800 0xFFFFFFFF
mww 0xF4000810 0xFFFFFFFF
mww 0xF4000820 0xFFFFFFFF
mww 0xF4000830 0xFFFFFFFF
echo "clocks has been enabled!"
}
$_TARGET0 configure -event reset-init {
init_clock
}

66
tcl/board/hpmicro/hpm5301evklite.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2023 HPMicro
adapter speed 10000
source [find interface/hpmicro/hpmicro_evk.cfg]
source [find target/hpmicro/hpm5300.cfg]
# openocd flash driver argument:
# - option0:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# [15:8] Dummy cycles
# 0 - Auto-probed / detected / default value
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
# [7:4] Misc.
# 0 - Not used
# 1 - SPI mode
# 2 - Internal loopback
# 3 - External DQS
# [3:0] Frequency option
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
# - option1:
# [31:20] Reserved
# [19:16] IO voltage
# 0 - 3V / 1 - 1.8V
# [15:12] Pin group
# 0 - 1st group / 1 - 2nd group
# [11:8] Connection selection
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
# [7:0] Drive Strength
# 0 - Default value
# xpi0 configs
# - flash driver: hpm_xpi
# - flash ctrl index: 0xF3000000
# - base address: 0x80000000
# - flash size: 0x2000000
# - flash option0: 0x5
# - flash option1: 0x1000
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000
proc init_clock {} {
mww 0xF4000800 0xFFFFFFFF
mww 0xF4000810 0xFFFFFFFF
mww 0xF4000820 0xFFFFFFFF
mww 0xF4000830 0xFFFFFFFF
echo "clocks has been enabled!"
}
$_TARGET0 configure -event reset-init {
init_clock
}

64
tcl/board/hpmicro/hpm6200evk.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2023 HPMicro
adapter speed 10000
source [find interface/hpmicro/hpmicro_evk.cfg]
source [find target/hpmicro/hpm6280-single-core.cfg]
# openocd flash driver argument:
# - option0:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# [15:8] Dummy cycles
# 0 - Auto-probed / detected / default value
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
# [7:4] Misc.
# 0 - Not used
# 1 - SPI mode
# 2 - Internal loopback
# 3 - External DQS
# [3:0] Frequency option
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
# - option1:
# [31:20] Reserved
# [19:16] IO voltage
# 0 - 3V / 1 - 1.8V
# [15:12] Pin group
# 0 - 1st group / 1 - 2nd group
# [11:8] Connection selection
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
# [7:0] Drive Strength
# 0 - Default value
# xpi0 configs
# - flash driver: hpm_xpi
# - flash ctrl index: 0xF3040000
# - base address: 0x80000000
# - flash size: 0x1000000
flash bank xpi0 hpm_xpi 0x80000000 0x1000000 0 0 $_TARGET0 0xF3040000
proc init_clock {} {
mww 0xF4000800 0xFFFFFFFF
mww 0xF4000810 0xFFFFFFFF
mww 0xF4000820 0xFFFFFFFF
mww 0xF4000830 0xFFFFFFFF
echo "clocks has been enabled!"
}
$_TARGET0 configure -event reset-init {
init_clock
}

217
tcl/board/hpmicro/hpm6300evk.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2021 HPMicro
adapter speed 10000
source [find interface/hpmicro/hpmicro_evk.cfg]
source [find target/hpmicro/hpm6360.cfg]
# openocd flash driver argument:
# - option0:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# openocd flash driver argument:
# - option0:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# [15:8] Dummy cycles
# 0 - Auto-probed / detected / default value
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
# [7:4] Misc.
# 0 - Not used
# 1 - SPI mode
# 2 - Internal loopback
# 3 - External DQS
# [3:0] Frequency option
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
# - option1:
# [31:20] Reserved
# [19:16] IO voltage
# 0 - 3V / 1 - 1.8V
# [15:12] Pin group
# 0 - 1st group / 1 - 2nd group
# [11:8] Connection selection
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
# [7:0] Drive Strength
# 0 - Default value
# xpi0 configs
# - flash driver: hpm_xpi
# - flash ctrl index: 0xF3040000
# - base address: 0x80000000
# - flash size: 0x1000000
flash bank xpi0 hpm_xpi 0x80000000 0x1000000 0 0 $_TARGET0 0xF3040000
proc init_clock {} {
mww 0xF4000800 0xFFFFFFFF
mww 0xF4000810 0xFFFFFFFF
mww 0xF4000820 0xFFFFFFFF
mww 0xF4000830 0xFFFFFFFF
echo "clocks has been enabled!"
}
proc init_sdram { } {
# configure femc frequency
# 166Mhz pll0_clk1: 333Mhz divide by 2
mww 0xF4001808 0x201
# PA25
mww 0xF40400C8 0xC
# PA26
mww 0xF40400D0 0xC
# PA27
mww 0xF40400D8 0xC
# PA28
mww 0xF40400E0 0xC
# PA29
mww 0xF40400E8 0xC
# PA30
mww 0xF40400F0 0xC
# PA31
mww 0xF40400F8 0xC
# PB00
mww 0xF4040100 0xC
# PB01
mww 0xF4040108 0xC
# PB02
mww 0xF4040110 0xC
# PB03
mww 0xF4040118 0xC
# PB04
mww 0xF4040120 0xC
# PB05
mww 0xF4040128 0xC
# PB06
mww 0xF4040130 0xC
# PB07
mww 0xF4040138 0xC
# PB08
mww 0xF4040140 0xC
# PB09
mww 0xF4040148 0xC
# PB10
mww 0xF4040150 0xC
# PB11
mww 0xF4040158 0xC
# PB12
mww 0xF4040160 0xC
# PB13
mww 0xF4040168 0xC
# PB14
mww 0xF4040170 0xC
# PB15
mww 0xF4040178 0xC
# PB16
mww 0xF4040180 0xC
# PB17
mww 0xF4040188 0xC
# PB18
mww 0xF4040190 0xC
# PB19
mww 0xF4040198 0xC
# PB20
mww 0xF40401A0 0xC
# PB21
mww 0xF40401A8 0xC
# PB22
mww 0xF40401B0 0xC
# PB23
mww 0xF40401B8 0xC
# PB24
mww 0xF40401C0 0xC
# PB25
mww 0xF40401C8 0xC
# PB26
mww 0xF40401D0 0xC
# PB27
mww 0xF40401D8 0xC
# PB28
mww 0xF40401E0 0xC
# PB29
mww 0xF40401E8 0xC
# PB30
mww 0xF40401F0 0xC
# PB31
mww 0xF40401F8 0xC
# femc configuration
mww 0xF3050000 0x1
sleep 10
mww 0xF3050000 0x2
mww 0xF3050008 0x30524
mww 0xF305000C 0x6030524
mww 0xF3050000 0x10000004
# 32MB
mww 0xF3050010 0x4000001b
mww 0xF3050014 0
# 16-bit
mww 0xF3050040 0xf31
# 166Mhz configuration
mww 0xF3050044 0x884e33
mww 0xF3050048 0x1020d0d
mww 0xF3050048 0x1020d0d
mww 0xF305004C 0x2020300
# config delay cell
mww 0xF3050150 0x2000
mww 0xF3050094 0
mww 0xF3050098 0
# precharge all
mww 0xF3050090 0x40000000
mww 0xF305009C 0xA55A000F
sleep 500
mww 0xF305003C 0x3
# auto refresh
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
# set mode
mww 0xF30500A0 0x33
mww 0xF305009C 0xA55A000A
sleep 500
mww 0xF305003C 0x3
mww 0xF305004C 0x2020301
echo "SDRAM has been initialized"
}
$_TARGET0 configure -event reset-init {
init_clock
init_sdram
}

239
tcl/board/hpmicro/hpm6750evk.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2021 HPMicro
adapter speed 10000
source [find interface/hpmicro/hpmicro_evk.cfg]
source [find target/hpmicro/hpm6750-single-core.cfg]
# openocd flash driver argument:
# - option0:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# [15:8] Dummy cycles
# 0 - Auto-probed / detected / default value
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
# [7:4] Misc.
# 0 - Not used
# 1 - SPI mode
# 2 - Internal loopback
# 3 - External DQS
# [3:0] Frequency option
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
# - option1:
# [31:20] Reserved
# [19:16] IO voltage
# 0 - 3V / 1 - 1.8V
# [15:12] Pin group
# 0 - 1st group / 1 - 2nd group
# [11:8] Connection selection
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
# [7:0] Drive Strength
# 0 - Default value
# xpi0 configs
# - flash driver: hpm_xpi
# - flash ctrl index: 0xF3040000
# - base address: 0x80000000
# - flash size: 0x2000000
# - flash option0: 0x7
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3040000 0x7
proc init_clock {} {
mww 0xF4000800 0xFFFFFFFF
mww 0xF4000810 0xFFFFFFFF
mww 0xF4000820 0xFFFFFFFF
mww 0xF4000830 0xFFFFFFFF
echo "clocks has been enabled!"
}
proc init_sdram { } {
# configure femc frequency
# 133Mhz pll1_clk0: 266Mhz divide by 2
#mww 0xF4001820 0x201
# 166Mhz pll2_clk0: 333Mhz divide by 2
mww 0xF4001820 0x401
# PC01
mww 0xF4040208 0xC
# PC00
mww 0xF4040200 0xC
# PB31
mww 0xF40401F8 0xC
# PB30
mww 0xF40401F0 0xC
# PB29
mww 0xF40401E8 0xC
# PB28
mww 0xF40401E0 0xC
# PB27
mww 0xF40401D8 0xC
# PB26
mww 0xF40401D0 0xC
# PB25
mww 0xF40401C8 0xC
# PB24
mww 0xF40401C0 0xC
# PB23
mww 0xF40401B8 0xC
# PB22
mww 0xF40401B0 0xC
# PB21
mww 0xF40401A8 0xC
# PB20
mww 0xF40401A0 0xC
# PB19
mww 0xF4040198 0xC
# PB18
mww 0xF4040190 0xC
# PD13
mww 0xF4040368 0xC
# PD12
mww 0xF4040360 0xC
# PD10
mww 0xF4040350 0xC
# PD09
mww 0xF4040348 0xC
# PD08
mww 0xF4040340 0xC
# PD07
mww 0xF4040338 0xC
# PD06
mww 0xF4040330 0xC
# PD05
mww 0xF4040328 0xC
# PD04
mww 0xF4040320 0xC
# PD03
mww 0xF4040318 0xC
# PD02
mww 0xF4040310 0xC
# PD01
mww 0xF4040308 0xC
# PD00
mww 0xF4040300 0xC
# PC29
mww 0xF40402E8 0xC
# PC28
mww 0xF40402E0 0xC
# PC27
mww 0xF40402D8 0xC
# PC22
mww 0xF40402B0 0xC
# PC21
mww 0xF40402A8 0xC
# PC17
mww 0xF4040288 0xC
# PC15
mww 0xF4040278 0xC
# PC12
mww 0xF4040260 0xC
# PC11
mww 0xF4040258 0xC
# PC10
mww 0xF4040250 0xC
# PC09
mww 0xF4040248 0xC
# PC08
mww 0xF4040240 0xC
# PC07
mww 0xF4040238 0xC
# PC06
mww 0xF4040230 0xC
# PC05
mww 0xF4040228 0xC
# PC04
mww 0xF4040220 0xC
# PC14
mww 0xF4040270 0xC
# PC13
mww 0xF4040268 0xC
# PC16
# mww 0xF4040280 0x1000C
# PC26
mww 0xF40402D0 0xC
# PC25
mww 0xF40402C8 0xC
# PC19
mww 0xF4040298 0xC
# PC18
mww 0xF4040290 0xC
# PC23
mww 0xF40402B8 0xC
# PC24
mww 0xF40402C0 0xC
# PC30
mww 0xF40402F0 0xC
# PC31
mww 0xF40402F8 0xC
# PC02
mww 0xF4040210 0xC
# PC03
mww 0xF4040218 0xC
# femc configuration
mww 0xF3050000 0x1
sleep 10
mww 0xF3050000 0x2
mww 0xF3050008 0x30524
mww 0xF305000C 0x6030524
mww 0xF3050000 0x10000000
mww 0xF3050010 0x4000001b
mww 0xF3050014 0
mww 0xF3050040 0xf32
# 133Mhz configuration
#mww 0xF3050044 0x884e22
# 166Mhz configuration
mww 0xF3050044 0x884e33
mww 0xF3050048 0x1020d0d
mww 0xF3050048 0x1020d0d
mww 0xF305004C 0x2020300
# config delay cell
mww 0xF3050150 0x3b
mww 0xF3050150 0x203b
mww 0xF3050094 0
mww 0xF3050098 0
# precharge all
mww 0xF3050090 0x40000000
mww 0xF305009C 0xA55A000F
sleep 500
mww 0xF305003C 0x3
# auto refresh
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
# set mode
mww 0xF30500A0 0x33
mww 0xF305009C 0xA55A000A
sleep 500
mww 0xF305003C 0x3
mww 0xF305004C 0x2020301
echo "SDRAM has been initialized"
}
$_TARGET0 configure -event reset-init {
init_clock
init_sdram
}

239
tcl/board/hpmicro/hpm6750evk2.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2022 HPMicro
adapter speed 10000
source [find interface/hpmicro/hpmicro_evk.cfg]
source [find target/hpmicro/hpm6750-single-core.cfg]
# openocd flash driver argument:
# - option0:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# [15:8] Dummy cycles
# 0 - Auto-probed / detected / default value
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
# [7:4] Misc.
# 0 - Not used
# 1 - SPI mode
# 2 - Internal loopback
# 3 - External DQS
# [3:0] Frequency option
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
# - option1:
# [31:20] Reserved
# [19:16] IO voltage
# 0 - 3V / 1 - 1.8V
# [15:12] Pin group
# 0 - 1st group / 1 - 2nd group
# [11:8] Connection selection
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
# [7:0] Drive Strength
# 0 - Default value
# xpi0 configs
# - flash driver: hpm_xpi
# - flash ctrl index: 0xF3040000
# - base address: 0x80000000
# - flash size: 0x2000000
# - flash option0: 0x7
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7
proc init_clock {} {
mww 0xF4000800 0xFFFFFFFF
mww 0xF4000810 0xFFFFFFFF
mww 0xF4000820 0xFFFFFFFF
mww 0xF4000830 0xFFFFFFFF
echo "clocks has been enabled!"
}
proc init_sdram { } {
# configure femc frequency
# 133Mhz pll1_clk0: 266Mhz divide by 2
#mww 0xF4001820 0x201
# 166Mhz pll2_clk0: 333Mhz divide by 2
mww 0xF4001820 0x401
# PC01
mww 0xF4040208 0xC
# PC00
mww 0xF4040200 0xC
# PB31
mww 0xF40401F8 0xC
# PB30
mww 0xF40401F0 0xC
# PB29
mww 0xF40401E8 0xC
# PB28
mww 0xF40401E0 0xC
# PB27
mww 0xF40401D8 0xC
# PB26
mww 0xF40401D0 0xC
# PB25
mww 0xF40401C8 0xC
# PB24
mww 0xF40401C0 0xC
# PB23
mww 0xF40401B8 0xC
# PB22
mww 0xF40401B0 0xC
# PB21
mww 0xF40401A8 0xC
# PB20
mww 0xF40401A0 0xC
# PB19
mww 0xF4040198 0xC
# PB18
mww 0xF4040190 0xC
# PD13
mww 0xF4040368 0xC
# PD12
mww 0xF4040360 0xC
# PD10
mww 0xF4040350 0xC
# PD09
mww 0xF4040348 0xC
# PD08
mww 0xF4040340 0xC
# PD07
mww 0xF4040338 0xC
# PD06
mww 0xF4040330 0xC
# PD05
mww 0xF4040328 0xC
# PD04
mww 0xF4040320 0xC
# PD03
mww 0xF4040318 0xC
# PD02
mww 0xF4040310 0xC
# PD01
mww 0xF4040308 0xC
# PD00
mww 0xF4040300 0xC
# PC29
mww 0xF40402E8 0xC
# PC28
mww 0xF40402E0 0xC
# PC27
mww 0xF40402D8 0xC
# PC22
mww 0xF40402B0 0xC
# PC21
mww 0xF40402A8 0xC
# PC17
mww 0xF4040288 0xC
# PC15
mww 0xF4040278 0xC
# PC12
mww 0xF4040260 0xC
# PC11
mww 0xF4040258 0xC
# PC10
mww 0xF4040250 0xC
# PC09
mww 0xF4040248 0xC
# PC08
mww 0xF4040240 0xC
# PC07
mww 0xF4040238 0xC
# PC06
mww 0xF4040230 0xC
# PC05
mww 0xF4040228 0xC
# PC04
mww 0xF4040220 0xC
# PC14
mww 0xF4040270 0xC
# PC13
mww 0xF4040268 0xC
# PC16
#mww 0xF4040280 0x1000C
# PC26
mww 0xF40402D0 0xC
# PC25
mww 0xF40402C8 0xC
# PC19
mww 0xF4040298 0xC
# PC18
mww 0xF4040290 0xC
# PC23
mww 0xF40402B8 0xC
# PC24
mww 0xF40402C0 0xC
# PC30
mww 0xF40402F0 0xC
# PC31
mww 0xF40402F8 0xC
# PC02
mww 0xF4040210 0xC
# PC03
mww 0xF4040218 0xC
# femc configuration
mww 0xF3050000 0x1
sleep 10
mww 0xF3050000 0x2
mww 0xF3050008 0x30524
mww 0xF305000C 0x6030524
mww 0xF3050000 0x10000000
mww 0xF3050010 0x4000001b
mww 0xF3050014 0
mww 0xF3050040 0xf32
# 133Mhz configuration
#mww 0xF3050044 0x884e22
# 166Mhz configuration
mww 0xF3050044 0x884e33
mww 0xF3050048 0x1020d0d
mww 0xF3050048 0x1020d0d
mww 0xF305004C 0x2020300
# config delay cell
mww 0xF3050150 0x3b
mww 0xF3050150 0x203b
mww 0xF3050094 0
mww 0xF3050098 0
# precharge all
mww 0xF3050090 0x40000000
mww 0xF305009C 0xA55A000F
sleep 500
mww 0xF305003C 0x3
# auto refresh
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
# set mode
mww 0xF30500A0 0x33
mww 0xF305009C 0xA55A000A
sleep 500
mww 0xF305003C 0x3
mww 0xF305004C 0x2020301
echo "SDRAM has been initialized"
}
$_TARGET0 configure -event reset-init {
init_clock
init_sdram
}

210
tcl/board/hpmicro/hpm6750evkmini.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2021 HPMicro
adapter speed 10000
source [find interface/hpmicro/hpmicro_evk.cfg]
source [find target/hpmicro/hpm6750-single-core.cfg]
# openocd flash driver argument:
# - ARG7:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# [15:8] Dummy cycles
# 0 - Auto-probed / detected / default value
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
# [7:4] Misc.
# 0 - Not used
# 1 - SPI mode
# 2 - Internal loopback
# 3 - External DQS
# [3:0] Frequency option
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
# - ARG8:
# [31:20] Reserved
# [19:16] IO voltage
# 0 - 3V / 1 - 1.8V
# [15:12] Pin group
# 0 - 1st group / 1 - 2nd group
# [11:8] Connection selection
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
# [7:0] Drive Strength
# 0 - Default value
# xpi0 configs
# - flash driver: hpm_xpi
# - flash ctrl index: 0xF3040000
# - base address: 0x80000000
# - flash size: 0x1000000
# - flash option0: 0x7
flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 0x7
proc init_clock {} {
mww 0xF4000800 0xFFFFFFFF
mww 0xF4000810 0xFFFFFFFF
mww 0xF4000820 0xFFFFFFFF
mww 0xF4000830 0xFFFFFFFF
echo "clocks has been enabled!"
}
proc init_sdram { } {
# configure femc frequency
# 133Mhz pll1_clk0: 266Mhz divide by 2
#mww 0xF4001820 0x201
# 166Mhz pll2_clk0: 333Mhz divide by 2
mww 0xF4001820 0x401
# PD13
mww 0xF4040368 0xC
# PD12
mww 0xF4040360 0xC
# PD10
mww 0xF4040350 0xC
# PD09
mww 0xF4040348 0xC
# PD08
mww 0xF4040340 0xC
# PD07
mww 0xF4040338 0xC
# PD06
mww 0xF4040330 0xC
# PD05
mww 0xF4040328 0xC
# PD04
mww 0xF4040320 0xC
# PD03
mww 0xF4040318 0xC
# PD02
mww 0xF4040310 0xC
# PD01
mww 0xF4040308 0xC
# PD00
mww 0xF4040300 0xC
# PC29
mww 0xF40402E8 0xC
# PC28
mww 0xF40402E0 0xC
# PC27
mww 0xF40402D8 0xC
# PC22
mww 0xF40402B0 0xC
# PC21
mww 0xF40402A8 0xC
# PC17
mww 0xF4040288 0xC
# PC15
mww 0xF4040278 0xC
# PC12
mww 0xF4040260 0xC
# PC11
mww 0xF4040258 0xC
# PC10
mww 0xF4040250 0xC
# PC09
mww 0xF4040248 0xC
# PC08
mww 0xF4040240 0xC
# PC07
mww 0xF4040238 0xC
# PC06
mww 0xF4040230 0xC
# PC05
mww 0xF4040228 0xC
# PC04
mww 0xF4040220 0xC
# PC14
mww 0xF4040270 0xC
# PC13
mww 0xF4040268 0xC
# PC16
#mww 0xF4040280 0x1000C
# PC26
mww 0xF40402D0 0xC
# PC25
mww 0xF40402C8 0xC
# PC19
mww 0xF4040298 0xC
# PC18
mww 0xF4040290 0xC
# PC23
mww 0xF40402B8 0xC
# PC24
mww 0xF40402C0 0xC
# PC30
mww 0xF40402F0 0xC
# PC31
mww 0xF40402F8 0xC
# PC02
mww 0xF4040210 0xC
# PC03
mww 0xF4040218 0xC
# femc configuration
mww 0xF3050000 0x1
sleep 10
mww 0xF3050000 0x2
mww 0xF3050008 0x30524
mww 0xF305000C 0x6030524
mww 0xF3050000 0x10000000
# 16MB
mww 0xF3050010 0x40000019
mww 0xF3050014 0
# 16-bit
mww 0xF3050040 0xf31
# 133Mhz configuration
#mww 0xF3050044 0x884e22
# 166Mhz configuration
mww 0xF3050044 0x884e33
mww 0xF3050048 0x1020d0d
mww 0xF3050048 0x1020d0d
mww 0xF305004C 0x2020300
# config delay cell
mww 0xF3050150 0x3b
mww 0xF3050150 0x203b
mww 0xF3050094 0
mww 0xF3050098 0
# precharge all
mww 0xF3050090 0x40000000
mww 0xF305009C 0xA55A000F
sleep 500
mww 0xF305003C 0x3
# auto refresh
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
mww 0xF305009C 0xA55A000C
sleep 500
mww 0xF305003C 0x3
# set mode
mww 0xF30500A0 0x33
mww 0xF305009C 0xA55A000A
sleep 500
mww 0xF305003C 0x3
mww 0xF305004C 0x2020301
echo "SDRAM has been initialized"
}
$_TARGET0 configure -event reset-init {
init_clock
init_sdram
}

157
tcl/board/hpmicro/hpm6800evk.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2023 HPMicro
adapter speed 10000
source [find interface/hpmicro/hpmicro_evk.cfg]
source [find target/hpmicro/hpm6880.cfg]
# openocd flash driver argument:
# - option0:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# [15:8] Dummy cycles
# 0 - Auto-probed / detected / default value
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
# [7:4] Misc.
# 0 - Not used
# 1 - SPI mode
# 2 - Internal loopback
# 3 - External DQS
# [3:0] Frequency option
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
# - option1:
# [31:20] Reserved
# [19:16] IO voltage
# 0 - 3V / 1 - 1.8V
# [15:12] Pin group
# 0 - 1st group / 1 - 2nd group
# [11:8] Connection selection
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
# [7:0] Drive Strength
# 0 - Default value
# xpi0 configs
# - flash driver: hpm_xpi
# - flash ctrl index: 0xF3000000
# - base address: 0x80000000
# - flash size: 0x2000000
# - flash option0: 0x7
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3000000 0x7
proc init_clock {} {
mww 0xF4000800 0xFFFFFFFF
mww 0xF4000810 0xFFFFFFFF
mww 0xF4000820 0xFFFFFFFF
mww 0xF4000830 0xFFFFFFFF
echo "clocks has been enabled!"
}
proc init_ddr3 {} {
# ddr dcdc setup
mww 0xF4104080 0x10578
# ddr3 setup
mww 0xF40C0180 0x30000019
mww 0xF400180C 0x09100401
mww 0xF4153000 0xF0000010
mww 0xF30101B0 0
mww 0xF4150040 0xf004641f
mww 0xF4153000 0xf0000011
mww 0xF3013000 0xf4000000
mww 0xF3010490 1
mww 0xF3010000 0x1040001
mww 0xF30100D0 0x4002004e
mww 0xF3010110 0x05010407
mww 0xF3010190 0x07040102
mww 0xF3010194 0x20404
mww 0xF30101A4 0x20008
mww 0xF3010240 0x06000600
mww 0xF3010200 0x1F1F1F
mww 0xF3010204 0x121212
mww 0xF3010208 0
mww 0xF301020C 0
mww 0xF3010210 0x1F1F
mww 0xF3010214 0x06030303
mww 0xF3010218 0x0F060606
mww 0xF3013000 0xFC000000
mww 0xF4150054 0xc70
mww 0xF4150058 0x6
mww 0xF415005c 0x18
mww 0xF4150048 0x919c8866
mww 0xF415004c 0x1a838360
mww 0xF415008c 0xf06d50
mww 0xF4150050 0x3002d200
mww 0xF30101b0 1
sleep 100
mww 0xF4150068 0x930035C7
mww 0xF4150004 0xFF81
sleep 200
echo "ddr3 has been enabled!"
}
proc init_dram {} {
# ddr dcdc setup
mww 0xF4104080 0x10708
# pll1 setup
mww 0xF40c0180 0xb0000016
mww 0xF40c0184 0
mww 0xF40c0188 0xe4e1c00
#ddr setup
mww 0xF3010000 0x3040000
mww 0xF30101B0 0
mww 0xF4150044 0x40a
mww 0xF4150040 0xf004641f
mww 0xF4153000 0xf0000011
mww 0xF3013000 0xf4000000
mww 0xF3010490 1
mww 0xF3010000 0x1040000
mww 0xF3010190 0x07010101
mww 0xF3010194 0x20404
mww 0xF30101A4 0x20008
mww 0xF3010240 0x6000600
mww 0xF3010200 0x1f1f1f
mww 0xF3010204 0x70707
mww 0xF3010208 0
mww 0xF301020c 0
mww 0xF3010210 0x1f1f
mww 0xF3010214 0x6060606
mww 0xF3010218 0xf0f0606
mww 0xF3013000 0xfc000000
mww 0xF4150020 0x3000100
mww 0xF4150028 0x18002356
mww 0xF415002c 0x0aac4156
mww 0xF4150054 0xe73
mww 0xF4150058 0x5
mww 0xF415005c 0
mww 0xF4150048 0xf2adfe53
mww 0xF415004c 0x22820362
mww 0xF4150050 0x30020100
mww 0xF415008c 0xf06d50
mww 0xF30101b0 1
sleep 100
mww 0xF4150068 0x91003587
mww 0xF4150004 0xF501
sleep 200
echo "ddr has been enabled!"
}
$_TARGET0 configure -event reset-init {
init_clock
init_ddr3
}

65
tcl/board/hpmicro/hpm6e00evk.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2024 HPMicro
adapter speed 10000
source [find interface/hpmicro/hpmicro_evk.cfg]
source [find target/hpmicro/hpm6e80-single-core.cfg]
# openocd flash driver argument:
# - option0:
# [31:28] Flash probe type
# 0 - SFDP SDR / 1 - SFDP DDR
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
# 6 - OctaBus DDR (SPI -> OPI DDR)
# 8 - Xccela DDR (SPI -> OPI DDR)
# 10 - EcoXiP DDR (SPI -> OPI DDR)
# [27:24] Command Pads after Power-on Reset
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [23:20] Command Pads after Configuring FLASH
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
# 0 - Not needed
# 1 - QE bit is at bit6 in Status Register 1
# 2 - QE bit is at bit1 in Status Register 2
# 3 - QE bit is at bit7 in Status Register 2
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
# [15:8] Dummy cycles
# 0 - Auto-probed / detected / default value
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
# [7:4] Misc.
# 0 - Not used
# 1 - SPI mode
# 2 - Internal loopback
# 3 - External DQS
# [3:0] Frequency option
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
# - option1:
# [31:20] Reserved
# [19:16] IO voltage
# 0 - 3V / 1 - 1.8V
# [15:12] Pin group
# 0 - 1st group / 1 - 2nd group
# [11:8] Connection selection
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
# [7:0] Drive Strength
# 0 - Default value
# xpi0 configs
# - flash driver: hpm_xpi
# - flash ctrl index: 0xF3000000
# - base address: 0x80000000
# - flash size: 0x2000000
# - flash option0: 0x7
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3000000 0x7
proc init_clock {} {
mww 0xF4000800 0xFFFFFFFF
mww 0xF4000810 0xFFFFFFFF
mww 0xF4000820 0xFFFFFFFF
mww 0xF4000830 0xFFFFFFFF
echo "clocks has been enabled!"
}
$_TARGET0 configure -event reset-init {
init_clock
}

9
tcl/interface/hpmicro/hpmicro_evk.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2021 HPMicro
adapter driver ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0208 0x020b
ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400
ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800

24
tcl/target/hpmicro/hpm5300.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2021 HPMicro
#
# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251126/HPM5300DSV012.pdf
if { [info exists CHIPNAME] } {
set _CHIP $CHIPNAME
} else {
set _CHIP hpm5361
}
set _CPUTAPID 0x1000563D
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGET0 $_CHIP.cpu0
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common.cfg]
source [find target/hpmicro/hpm_common_csr_lite.cfg]
proc reset_soc {} {
sba_write_mem 0xF410001C 24000000
}

43
tcl/target/hpmicro/hpm6280-dual-core.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2021 HPMicro
#
# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM6200DSV26.pdf
if { [info exists CHIPNAME] } {
set _CHIP $CHIPNAME
} else {
set _CHIP hpm6280
}
set _CPUTAPID 0x1000563D
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGET0 $_CHIP.cpu0
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common.cfg]
source [find target/hpmicro/hpm_common_csr.cfg]
proc release_core1 {} {
sba_write_mem 0xF4002C00 0x1000
}
set _TARGET1 $_CHIP.cpu1
target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common_csr.cfg]
$_TARGET1 configure -event examine-start {
release_core1
}
$_TARGET1 configure -event reset-deassert-pre {
$::_TARGET0 arp_poll
release_core1
}
proc reset_soc {} {
sba_write_mem 0xF40C001C 24000000
}

24
tcl/target/hpmicro/hpm6280-single-core.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2021 HPMicro
#
# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM6200DSV26.pdf
if { [info exists CHIPNAME] } {
set _CHIP $CHIPNAME
} else {
set _CHIP hpm6280
}
set _CPUTAPID 0x1000563D
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGET0 $_CHIP.cpu0
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common.cfg]
source [find target/hpmicro/hpm_common_csr.cfg]
proc reset_soc {} {
sba_write_mem 0xF40C001C 24000000
}

24
tcl/target/hpmicro/hpm6360.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2021 HPMicro
#
# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM6300DSV28-779.pdf:w
if { [info exists CHIPNAME] } {
set _CHIP $CHIPNAME
} else {
set _CHIP hpm6360
}
set _CPUTAPID 0x1000563D
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGET0 $_CHIP.cpu0
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common.cfg]
source [find target/hpmicro/hpm_common_csr.cfg]
proc reset_soc {} {
sba_write_mem 0xF40C001C 24000000
}

55
tcl/target/hpmicro/hpm6750-dual-core.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2021 HPMicro
#
# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM67006400DSV27.pdf
if { [info exists CHIPNAME] } {
set _CHIP $CHIPNAME
} else {
set _CHIP hpm6750
}
set _CPUTAPID 0x1000563D
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGET0 $_CHIP.cpu0
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common.cfg]
source [find target/hpmicro/hpm_common_csr.cfg]
proc release_core1 {} {
set chip_rev [sba_read_mem 0x2001FF00]
if {$chip_rev != 0x56010100 } {
# set start point for core1
sba_write_mem 0xF4002C08 0x20016284
} else {
sba_write_mem 0xF4002C08 0x2001660c
}
# set boot flag for core1
sba_write_mem 0xF4002C0C 0xC1BEF1A9
# release core1
sba_write_mem 0xF4002C00 0x1000
}
set _TARGET1 $_CHIP.cpu1
target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common_csr.cfg]
$_TARGET1 configure -event examine-start {
release_core1
}
$_TARGET1 configure -event reset-deassert-pre {
$::_TARGET0 arp_poll
release_core1
}
proc reset_soc {} {
sba_write_mem 0xF40C001C 24000000
}

24
tcl/target/hpmicro/hpm6750-single-core.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2021 HPMicro
#
# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM67006400DSV27.pdf
if { [info exists CHIPNAME] } {
set _CHIP $CHIPNAME
} else {
set _CHIP hpm6750
}
set _CPUTAPID 0x1000563D
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGET0 $_CHIP.cpu0
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common.cfg]
source [find target/hpmicro/hpm_common_csr.cfg]
proc reset_soc {} {
sba_write_mem 0xF40C001C 24000000
}

24
tcl/target/hpmicro/hpm6880.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2023 HPMicro
#
# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251128/HPM6800DSV12.pdf
if { [info exists CHIPNAME] } {
set _CHIP $CHIPNAME
} else {
set _CHIP hpm6880
}
set _CPUTAPID 0x1000563D
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGET0 $_CHIP.cpu0
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common.cfg]
source [find target/hpmicro/hpm_common_csr.cfg]
proc reset_soc {} {
sba_write_mem 0xF410001C 24000000
}

47
tcl/target/hpmicro/hpm6e80-dual-core.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2024 HPMicro
#
# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM6E00DSV011.pdf
if { [info exists CHIPNAME] } {
set _CHIP $CHIPNAME
} else {
set _CHIP hpm6e00
}
set _CPUTAPID 0x1000563D
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGET0 $_CHIP.cpu0
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common.cfg]
source [find target/hpmicro/hpm_common_csr.cfg]
proc release_core1 {} {
sba_write_mem 0xF4002C00 0x1000
}
set _TARGET1 $_CHIP.cpu1
target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common_csr.cfg]
$_TARGET1 configure -event examine-start {
release_core1
}
$_TARGET1 configure -event reset-deassert-pre {
$::_TARGET0 arp_poll
release_core1
}
$_TARGET0 configure -event reset-end {
sba_write_mem 0xF4002010 0x2
}
proc reset_soc {} {
sba_write_mem 0xF410001C 24000000
}

24
tcl/target/hpmicro/hpm6e80-single-core.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2024 HPMicro
#
# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM6E00DSV011.pdf
if { [info exists CHIPNAME] } {
set _CHIP $CHIPNAME
} else {
set _CHIP hpm6e00
}
set _CPUTAPID 0x1000563D
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGET0 $_CHIP.cpu0
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
source [find target/hpmicro/hpm_common.cfg]
source [find target/hpmicro/hpm_common_csr.cfg]
proc reset_soc {} {
sba_write_mem 0xF410001C 24000000
}

29
tcl/target/hpmicro/hpm_common.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2025 HPMicro
source [find target/hpmicro/hpm_reset.cfg]
set dmsbcs 0x38
set dmsbaddress0 0x39
set dmsbdata0 0x3C
proc target0_dmi_write_reg {reg value} {
$::_TARGET0 riscv dmi_write ${reg} ${value}
}
proc target0_dmi_read_reg {reg} {
set v [$::_TARGET0 riscv dmi_read ${reg} $::dmsbdata0]
return ${v}
}
proc sba_write_mem {addr value} {
target0_dmi_write_reg $::dmsbaddress0 ${addr}
target0_dmi_write_reg $::dmsbdata0 ${value}
}
proc sba_read_mem {addr} {
set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }]
target0_dmi_write_reg $::dmsbcs ${sbcs}
target0_dmi_write_reg $::dmsbaddress0 ${addr}
set value [target0_dmi_read_reg $::dmsbdata0]
return ${value}
}

104
tcl/target/hpmicro/hpm_common_csr.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2024 HPMicro
# expose non-standard csr registers
# scounteren
riscv expose_csrs 262
# mcountinhibit
riscv expose_csrs 800
# milmb
riscv expose_csrs 1984
# mdlmb
riscv expose_csrs 1985
# mecc_code
riscv expose_csrs 1986
# mnvec
riscv expose_csrs 1987
# mxstatus
riscv expose_csrs 1988
# mpft_ctl
riscv expose_csrs 1989
# mhsp_ctl
riscv expose_csrs 1990
# msp_bound
riscv expose_csrs 1991
# msp_base
riscv expose_csrs 1992
# mdcause
riscv expose_csrs 1993
# mcache_ctl
riscv expose_csrs 1994
# mcctlbeginaddr
riscv expose_csrs 1995
# mcctlcommand
riscv expose_csrs 1996
# mcctldata
riscv expose_csrs 1997
# mcounterwen
riscv expose_csrs 1998
# mcounterinten
riscv expose_csrs 1999
# mmisc_ctl
riscv expose_csrs 2000
# mcountermask_m
riscv expose_csrs 2001
# mcountermask_s
riscv expose_csrs 2002
# mcountermask_u
riscv expose_csrs 2003
# mcounterovf
riscv expose_csrs 2004
# mslideleg
riscv expose_csrs 2005
# mclk_ctl
riscv expose_csrs 2015
# dexc2dbg
riscv expose_csrs 2016
# ddcause
riscv expose_csrs 2017
# uitb
riscv expose_csrs 2048
# ucode
riscv expose_csrs 2049
# udcause
riscv expose_csrs 2057
# ucctlbeginaddr
riscv expose_csrs 2059
# ucctlcommand
riscv expose_csrs 2060
# slie
riscv expose_csrs 2500
# slip
riscv expose_csrs 2501
# sdcause
riscv expose_csrs 2505
# scctldata
riscv expose_csrs 2509
# scounterinten
riscv expose_csrs 2511
# scountermask_m
riscv expose_csrs 2513
# scountermask_s
riscv expose_csrs 2514
# scountermask_u
riscv expose_csrs 2515
# scounterovf
riscv expose_csrs 2516
# scountinhibit
riscv expose_csrs 2528
# shpmevent3
riscv expose_csrs 2531
# shpmevent4
riscv expose_csrs 2532
# shpmevent5
riscv expose_csrs 2533
# shpmevent6
riscv expose_csrs 2534
# micm_cfg
riscv expose_csrs 4032
# mdcm_cfg
riscv expose_csrs 4033
# mmsc_cfg
riscv expose_csrs 4034
# mmsc_cfg2
riscv expose_csrs 4035

70
tcl/target/hpmicro/hpm_common_csr_lite.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2024 HPMicro
# expose non-standard csr registers
# mcountinhibit
riscv expose_csrs 800
# milmb
riscv expose_csrs 1984
# mdlmb
riscv expose_csrs 1985
# mecc_code
riscv expose_csrs 1986
# mnvec
riscv expose_csrs 1987
# mxstatus
riscv expose_csrs 1988
# mpft_ctl
riscv expose_csrs 1989
# mhsp_ctl
riscv expose_csrs 1990
# msp_bound
riscv expose_csrs 1991
# msp_base
riscv expose_csrs 1992
# mdcause
riscv expose_csrs 1993
# mcache_ctl
riscv expose_csrs 1994
# mcctlbeginaddr
riscv expose_csrs 1995
# mcctlcommand
riscv expose_csrs 1996
# mcctldata
riscv expose_csrs 1997
# mcounterwen
riscv expose_csrs 1998
# mcounterinten
riscv expose_csrs 1999
# mmisc_ctl
riscv expose_csrs 2000
# mcountermask_m
riscv expose_csrs 2001
# mcountermask_s
riscv expose_csrs 2002
# mcountermask_u
riscv expose_csrs 2003
# mcounterovf
riscv expose_csrs 2004
# dexc2dbg
riscv expose_csrs 2016
# ddcause
riscv expose_csrs 2017
# uitb
riscv expose_csrs 2048
# ucode
riscv expose_csrs 2049
# udcause
riscv expose_csrs 2057
# ucctlbeginaddr
riscv expose_csrs 2059
# ucctlcommand
riscv expose_csrs 2060
# micm_cfg
riscv expose_csrs 4032
# mdcm_cfg
riscv expose_csrs 4033
# mmsc_cfg
riscv expose_csrs 4034
# mmsc_cfg2
riscv expose_csrs 4035

13
tcl/target/hpmicro/hpm_reset.cfg Normal file
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# SPDX-License-Identifier: BSD-3-Clause
# Copyright (c) 2025 HPMicro
# As debug access needs to be released by bootrom after reset,
# and halt request set along with reset will be ignored, it needs
# a short period of time for bootrom to release the access,
# so we request halt again in reset-deassert-pre event.
$_TARGET0 configure -event reset-deassert-pre {
sleep 1
if {$halt} {
$::_TARGET0 arp_halt
}
}