forked from auracaster/openocd
0e2f990c87
- add board and device config files - add interface config file for hpmicro evk boards Change-Id: I8afb0b734b1064d71c4af3c118c7777d0ead9e6b Signed-off-by: Ryan QIAN <jianghao.qian@hpmicro.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8697 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
158 lines
4.3 KiB
INI
158 lines
4.3 KiB
INI
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (c) 2023 HPMicro
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adapter speed 10000
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source [find interface/hpmicro/hpmicro_evk.cfg]
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source [find target/hpmicro/hpm6880.cfg]
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# openocd flash driver argument:
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# - option0:
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# [31:28] Flash probe type
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# 0 - SFDP SDR / 1 - SFDP DDR
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# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
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# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
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# 6 - OctaBus DDR (SPI -> OPI DDR)
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# 8 - Xccela DDR (SPI -> OPI DDR)
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# 10 - EcoXiP DDR (SPI -> OPI DDR)
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# [27:24] Command Pads after Power-on Reset
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# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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# [23:20] Command Pads after Configuring FLASH
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# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
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# 0 - Not needed
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# 1 - QE bit is at bit6 in Status Register 1
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# 2 - QE bit is at bit1 in Status Register 2
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# 3 - QE bit is at bit7 in Status Register 2
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# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
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# [15:8] Dummy cycles
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# 0 - Auto-probed / detected / default value
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# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
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# [7:4] Misc.
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# 0 - Not used
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# 1 - SPI mode
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# 2 - Internal loopback
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# 3 - External DQS
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# [3:0] Frequency option
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# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
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# - option1:
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# [31:20] Reserved
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# [19:16] IO voltage
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# 0 - 3V / 1 - 1.8V
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# [15:12] Pin group
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# 0 - 1st group / 1 - 2nd group
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# [11:8] Connection selection
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# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
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# [7:0] Drive Strength
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# 0 - Default value
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# xpi0 configs
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# - flash driver: hpm_xpi
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# - flash ctrl index: 0xF3000000
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# - base address: 0x80000000
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# - flash size: 0x2000000
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# - flash option0: 0x7
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flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3000000 0x7
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proc init_clock {} {
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mww 0xF4000800 0xFFFFFFFF
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mww 0xF4000810 0xFFFFFFFF
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mww 0xF4000820 0xFFFFFFFF
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mww 0xF4000830 0xFFFFFFFF
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echo "clocks has been enabled!"
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}
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proc init_ddr3 {} {
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# ddr dcdc setup
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mww 0xF4104080 0x10578
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# ddr3 setup
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mww 0xF40C0180 0x30000019
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mww 0xF400180C 0x09100401
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mww 0xF4153000 0xF0000010
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mww 0xF30101B0 0
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mww 0xF4150040 0xf004641f
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mww 0xF4153000 0xf0000011
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mww 0xF3013000 0xf4000000
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mww 0xF3010490 1
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mww 0xF3010000 0x1040001
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mww 0xF30100D0 0x4002004e
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mww 0xF3010110 0x05010407
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mww 0xF3010190 0x07040102
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mww 0xF3010194 0x20404
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mww 0xF30101A4 0x20008
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mww 0xF3010240 0x06000600
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mww 0xF3010200 0x1F1F1F
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mww 0xF3010204 0x121212
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mww 0xF3010208 0
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mww 0xF301020C 0
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mww 0xF3010210 0x1F1F
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mww 0xF3010214 0x06030303
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mww 0xF3010218 0x0F060606
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mww 0xF3013000 0xFC000000
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mww 0xF4150054 0xc70
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mww 0xF4150058 0x6
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mww 0xF415005c 0x18
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mww 0xF4150048 0x919c8866
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mww 0xF415004c 0x1a838360
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mww 0xF415008c 0xf06d50
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mww 0xF4150050 0x3002d200
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mww 0xF30101b0 1
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sleep 100
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mww 0xF4150068 0x930035C7
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mww 0xF4150004 0xFF81
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sleep 200
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echo "ddr3 has been enabled!"
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}
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proc init_dram {} {
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# ddr dcdc setup
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mww 0xF4104080 0x10708
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# pll1 setup
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mww 0xF40c0180 0xb0000016
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mww 0xF40c0184 0
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mww 0xF40c0188 0xe4e1c00
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#ddr setup
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mww 0xF3010000 0x3040000
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mww 0xF30101B0 0
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mww 0xF4150044 0x40a
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mww 0xF4150040 0xf004641f
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mww 0xF4153000 0xf0000011
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mww 0xF3013000 0xf4000000
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mww 0xF3010490 1
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mww 0xF3010000 0x1040000
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mww 0xF3010190 0x07010101
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mww 0xF3010194 0x20404
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mww 0xF30101A4 0x20008
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mww 0xF3010240 0x6000600
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mww 0xF3010200 0x1f1f1f
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mww 0xF3010204 0x70707
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mww 0xF3010208 0
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mww 0xF301020c 0
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mww 0xF3010210 0x1f1f
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mww 0xF3010214 0x6060606
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mww 0xF3010218 0xf0f0606
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mww 0xF3013000 0xfc000000
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mww 0xF4150020 0x3000100
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mww 0xF4150028 0x18002356
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mww 0xF415002c 0x0aac4156
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mww 0xF4150054 0xe73
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mww 0xF4150058 0x5
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mww 0xF415005c 0
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mww 0xF4150048 0xf2adfe53
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mww 0xF415004c 0x22820362
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mww 0xF4150050 0x30020100
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mww 0xF415008c 0xf06d50
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mww 0xF30101b0 1
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sleep 100
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mww 0xF4150068 0x91003587
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mww 0xF4150004 0xF501
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sleep 200
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echo "ddr has been enabled!"
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}
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$_TARGET0 configure -event reset-init {
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init_clock
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init_ddr3
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}
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