forked from auracaster/openocd
tcl/target/rp2350: universal config for any combination of CM/RV cores
RP2350 has 2 slots where either Cortex-M33 or RISC-V can be selected. Tcl variable USE_CORE selects what cores will be configured for debug. Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Change-Id: I56fe1aa94304bdfd1ec98bba57cc3fa792a35f69 Reviewed-on: https://review.openocd.org/c/openocd/+/8449 Tested-by: jenkins
This commit is contained in:
Tomas Vanek
206
tcl/target/rp2350.cfg
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206
tcl/target/rp2350.cfg
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# SPDX-License-Identifier: GPL-2.0-or-later
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# RP2350 is a microcontroller with dual Cortex-M33 cores or dual Hazard3 RISC-V cores.
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# https://www.raspberrypi.com/documentation/microcontrollers/rp2350.html
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transport select swd
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME rp2350
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}
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x00040927
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}
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# Set to '1' to start rescue mode
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if { [info exists RESCUE] } {
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set _RESCUE $RESCUE
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} else {
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set _RESCUE 0
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}
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# Set to 'cm0' or 'cm1' for Cortex-M33 single core configuration
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# To keep compatibility with RP2040 aliases '0' and '1' are provided for Cortex-M33 cores
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# Use 'rv0' or 'rv1' for RISC-V single core configuration
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# List more for a multicore configuration
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if { [info exists USE_CORE] } {
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set _USE_CORE $USE_CORE
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} else {
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# defaults to both Cortex-M33 cores
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set _USE_CORE { cm0 cm1 }
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}
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swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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if { [info exists SWD_MULTIDROP] } {
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dap create $_CHIPNAME.dap -adiv6 -chain-position $_CHIPNAME.cpu -dp-id 0x0040927 -instance-id 0
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} else {
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dap create $_CHIPNAME.dap -adiv6 -chain-position $_CHIPNAME.cpu
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}
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# Cortex-M33 core 0
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if { [lsearch $_USE_CORE cm0] >= 0 || [lsearch $_USE_CORE 0] >= 0 } {
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set _TARGETNAME_CM0 $_CHIPNAME.cm0
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set _TARGETNAME_0 $_TARGETNAME_CM0
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}
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# RISC-V core 0
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if { [lsearch $_USE_CORE rv0] >= 0 } {
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set _TARGETNAME_RV0 $_CHIPNAME.rv0
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if { ![info exists _TARGETNAME_0] } {
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set _TARGETNAME_0 $_TARGETNAME_RV0
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}
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}
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# Cortex-M33 core 1
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if { [lsearch $_USE_CORE cm1] >= 0 || [lsearch $_USE_CORE 1] >= 0 } {
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set _TARGETNAME_CM1 $_CHIPNAME.cm1
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set _TARGETNAME_1 $_TARGETNAME_CM1
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}
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# RISC-V core 1
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if { [lsearch $_USE_CORE rv1] >= 0 } {
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set _TARGETNAME_RV1 $_CHIPNAME.rv1
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if { ![info exists _TARGETNAME_1] } {
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set _TARGETNAME_1 $_TARGETNAME_RV1
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}
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}
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if { [info exists _TARGETNAME_CM0] } {
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target create $_TARGETNAME_CM0 cortex_m -dap $_CHIPNAME.dap -ap-num 0x2000
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# srst does not exist; use SYSRESETREQ to perform a soft reset
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$_TARGETNAME_CM0 cortex_m reset_config sysresetreq
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# After a rescue reset the cache requires invalidate to allow SPI flash
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# reads from the XIP cached mapping area
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$_TARGETNAME_CM0 configure -event reset-init { rp2xxx rom_api_call FC }
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}
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if { [info exists _TARGETNAME_RV0] } {
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target create $_TARGETNAME_RV0 riscv -dap $_CHIPNAME.dap -ap-num 0xa000 -coreid 0
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$_TARGETNAME_RV0 riscv set_enable_virt2phys off
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# Workaround for stray IO_QSPI: GPIO_QSPI_SD1_CTRL: INOVER bit in RISC-V BOOTSEL
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$_TARGETNAME_RV0 configure -event reset-init { mww 0x4003002c 0 }
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if { [info exists _TARGETNAME_CM0] } {
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# just for setting after init when the event become-available is not fired
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$_TARGETNAME_RV0 configure -event examine-end "rp2xxx _switch_target $_TARGETNAME_CM0 $_TARGETNAME_RV0"
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}
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}
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if { [info exists _TARGETNAME_CM1] } {
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target create $_TARGETNAME_CM1 cortex_m -dap $_CHIPNAME.dap -ap-num 0x4000
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$_TARGETNAME_CM1 cortex_m reset_config sysresetreq
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}
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if { [info exists _TARGETNAME_RV1] } {
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target create $_TARGETNAME_RV1 riscv -dap $_CHIPNAME.dap -ap-num 0xa000 -coreid 1
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$_TARGETNAME_RV1 riscv set_enable_virt2phys off
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}
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if { [info exists USE_SMP] } {
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set _USE_SMP $USE_SMP
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} elseif { [info exists _TARGETNAME_CM0] == [info exists _TARGETNAME_CM1]
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&& [info exists _TARGETNAME_RV0] == [info exists _TARGETNAME_RV1] } {
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set _USE_SMP 1
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} else {
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set _USE_SMP 0
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}
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if { $_USE_SMP } {
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if { [info exists _TARGETNAME_CM0] && [info exists _TARGETNAME_CM1] } {
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$_TARGETNAME_CM0 configure -rtos hwthread
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$_TARGETNAME_CM1 configure -rtos hwthread
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target smp $_TARGETNAME_CM0 $_TARGETNAME_CM1
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}
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if { [info exists _TARGETNAME_RV0] && [info exists _TARGETNAME_RV1] } {
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$_TARGETNAME_RV0 configure -rtos hwthread
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$_TARGETNAME_RV1 configure -rtos hwthread
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target smp $_TARGETNAME_RV0 $_TARGETNAME_RV1
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}
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}
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if { [info exists _TARGETNAME_0] } {
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set _FLASH_TARGET $_TARGETNAME_0
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}
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if { ![info exists _FLASH_TARGET] && [info exists _TARGETNAME_1] } {
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set _FLASH_TARGET $_TARGETNAME_1
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if { [info exists _TARGETNAME_CM1] && [info exists _TARGETNAME_RV1] } {
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echo "Info : $_CHIPNAME.flash will be handled by $_TARGETNAME_1 without switching"
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}
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}
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if { [info exists _FLASH_TARGET] } {
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$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE
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if { [info exists _TARGETNAME_CM0] && [info exists _TARGETNAME_RV0] } {
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$_TARGETNAME_RV0 configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE
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echo "Info : $_CHIPNAME.flash will be handled by the active one of $_FLASH_TARGET and $_TARGETNAME_RV0 cores"
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}
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set _FLASHNAME $_CHIPNAME.flash
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set _FLASHSIZE 0x00400000
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flash bank $_FLASHNAME rp2040_flash 0x10000000 $_FLASHSIZE 0 0 $_FLASH_TARGET
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}
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if { [info exists _TARGETNAME_1] } {
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# Alias to ensure gdb connecting to core 1 gets the correct memory map
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flash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME
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}
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if { [info exists _TARGETNAME_0] } {
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# Select core 0
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targets $_TARGETNAME_0
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}
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# Cold reset resets everything except DP
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proc cold_reset { { __CHIPNAME "" } } {
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if { $__CHIPNAME == "" } {
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global _CHIPNAME
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set __CHIPNAME $_CHIPNAME
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}
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poll off
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# set CDBGRSTREQ (and keep set CSYSPWRUPREQ and CDBGPWRUPREQ)
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$__CHIPNAME.dap dpreg 4 0x54000000
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set dpstat [$__CHIPNAME.dap dpreg 4]
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if { [expr { $dpstat & 0xcc000000 }] != 0xcc000000 } {
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echo "Warn : dpstat_reset failed, DP STAT $dpstat"
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}
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$__CHIPNAME.dap dpreg 4 0x50000000
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dap init
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poll on
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}
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# Rescue reset resets everything except DP and RP_AP
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# Both Cortex-M33 cores stop in bootrom
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proc rescue_reset { { __CHIPNAME "" } } {
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if { $__CHIPNAME == "" } {
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global _CHIPNAME
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set __CHIPNAME $_CHIPNAME
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}
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poll off
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# set bit RESCUE_RESTART in RP_AP: CTRL register
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$__CHIPNAME.dap apreg 0x80000 0 0x80000000
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$__CHIPNAME.dap apreg 0x80000 0 0
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dap init
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poll on
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if { [lsearch [target names] $__CHIPNAME.cm0] < 0 } {
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echo "Info : restart OpenOCD with 'set USE_CORE { cm0 cm1 }' to debug after rescue"
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}
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}
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if { $_RESCUE } {
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init
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rescue_reset
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}
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