forked from auracaster/openocd
tcl/target/max32xxx: Update max32xxx tcl files to use new flashing algorithm
The max32xxx tcl files have been updated to work with the new flashing algorithm. A new max32xxx.cfg file contains common configuration and functionality. Change-Id: Ifaed58836d221ece6192faafa382b30fb72c77a6 Signed-off-by: Henrik Mau <henrik.mau@analog.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8976 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Henrik Mau
committed by
Antonio Borneo
Antonio Borneo
parent
ff550ed0b0
commit
a0ee225618
@@ -1,32 +1,20 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Maxim Integrated MAX32620 OpenOCD target configuration file
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# www.maximintegrated.com
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# adapter speed
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adapter speed 4000
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# reset pin configuration
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# Set the reset pin configuration
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reset_config srst_only
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adapter srst delay 200
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if {[using_jtag]} {
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jtag newtap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
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jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
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} else {
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swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
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}
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# Set flash parameters
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set FLASH_BASE 0x0
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set FLASH_SIZE 0x200000
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set FLC_BASE 0x40002000
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set FLASH_SECTOR 0x2000
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set FLASH_CLK 96
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set FLASH_OPTIONS 0x00
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dap create max32620.dap -chain-position max32620.cpu
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# Setup the reserved TAP
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set RSV_TAP 1
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# target configuration
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target create max32620.cpu cortex_m -dap max32620.dap
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max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
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# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
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# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
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# max32620 flash base address 0x00000000
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# max32620 flash size 0x200000 (2MB)
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# max32620 FLC base address 0x40002000
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# max32620 sector (page) size 0x2000 (8kB)
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# max32620 clock speed 96 (MHz)
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flash bank max32620.flash max32xxx 0x00000000 0x200000 0 0 max32620.cpu 0x40002000 0x2000 96
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source [find target/max32xxx_common.cfg]
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@@ -1,32 +1,20 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Maxim Integrated MAX32625 OpenOCD target configuration file
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# www.maximintegrated.com
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# adapter speed
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adapter speed 4000
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# reset pin configuration
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# Set the reset pin configuration
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reset_config srst_only
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adapter srst delay 200
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if {[using_jtag]} {
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jtag newtap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
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jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f71197 -ignore-version
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} else {
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swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
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}
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# Set flash parameters
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set FLASH_BASE 0x0
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set FLASH_SIZE 0x80000
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set FLC_BASE 0x40002000
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set FLASH_SECTOR 0x2000
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set FLASH_CLK 96
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set FLASH_OPTIONS 0x00
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dap create max32625.dap -chain-position max32625.cpu
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# Setup the reserved TAP
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set RSV_TAP 1
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# target configuration
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target create max32625.cpu cortex_m -dap max32625.dap
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max32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
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# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
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# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
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# max32625 flash base address 0x00000000
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# max32625 flash size 0x80000 (512k)
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# max32625 FLC base address 0x40002000
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# max32625 sector (page) size 0x2000 (8kB)
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# max32625 clock speed 96 (MHz)
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flash bank max32625.flash max32xxx 0x00000000 0x80000 0 0 max32625.cpu 0x40002000 0x2000 96
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source [find target/max32xxx_common.cfg]
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@@ -1,32 +1,40 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Maxim Integrated MAX3263X OpenOCD target configuration file
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# www.maximintegrated.com
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# adapter speed
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adapter speed 4000
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# Set the reset pin configuration
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reset_config none
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# reset pin configuration
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reset_config srst_only
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# Set flash parameters
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set FLASH_BASE 0x0
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set FLASH_SIZE 0x200000
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set FLC_BASE 0x40002000
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set FLASH_SECTOR 0x2000
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set FLASH_CLK 96
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set FLASH_OPTIONS 0x00
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if {[using_jtag]} {
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jtag newtap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
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jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f76197 -ignore-version
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} else {
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swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
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# Setup the reserved TAP
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set RSV_TAP 1
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source [find target/max32xxx_common.cfg]
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# Create custom reset sequence
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$_CHIPNAME.cpu configure -event reset-init {
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# Reset the peripherals
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mww 0x40000848 0xFFFFFFFF
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mww 0x4000084C 0xFFFFFFFF
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sleep 10
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mww 0x40000848 0x0
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mww 0x4000084C 0x0
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# Reset the SP
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set SP_ADDR [mrw 0x0]
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reg sp $SP_ADDR
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# Reset the PC to the Reset_Handler
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set RESET_HANDLER_ADDR [mrw 0x4]
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reg pc $RESET_HANDLER_ADDR
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}
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dap create max3263x.dap -chain-position max3263x.cpu
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# target configuration
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target create max3263x.cpu cortex_m -dap max3263x.dap
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max3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
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# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
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# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
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# max3263x flash base address 0x00000000
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# max3263x flash size 0x200000 (2MB)
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# max3263x FLC base address 0x40002000
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# max3263x sector (page) size 0x2000 (8kB)
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# max3263x clock speed 96 (MHz)
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flash bank max3263x.flash max32xxx 0x00000000 0x200000 0 0 max3263x.cpu 0x40002000 0x2000 96
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132
tcl/target/max32xxx_common.cfg
Normal file
132
tcl/target/max32xxx_common.cfg
Normal file
@@ -0,0 +1,132 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Maxim Integrated max32xxx OpenOCD driver configuration file.
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# Contains common settings for max32xxx devices.
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source [find mem_helper.tcl]
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source [find target/swj-dp.tcl]
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# Set the adapter speed
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if { [info exists ADAPTER_KHZ] } {
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set _ADAPTER_KHZ $ADAPTER_KHZ
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} else {
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set _ADAPTER_KHZ 2000
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}
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adapter speed $_ADAPTER_KHZ
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# Target configuration
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME max32xxx
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}
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# Add reserved TAP
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if { [using_jtag] && [info exists RSV_TAP] } {
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version
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jtag newtap rsvtap tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
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} else {
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version
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}
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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target create $_CHIPNAME.cpu cortex_m -dap $_CHIPNAME.dap
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# Enable thread-aware debugging
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$_CHIPNAME.cpu configure -rtos hwthread
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# Setup working area
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if { [info exists WORK_START] } {
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set _WORK_START $WORK_START
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} else {
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set _WORK_START 0x20005000
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}
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if { [info exists WORK_SIZE] } {
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set _WORK_SIZE $WORK_SIZE
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} else {
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set _WORK_SIZE 0x8000
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}
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$_CHIPNAME.cpu configure -work-area-phys $_WORK_START -work-area-size $_WORK_SIZE
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# Configure flash driver
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if { [info exists FLASH_BASE] } {
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set _FLASH_BASE $FLASH_BASE
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} else {
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set _FLASH_BASE 0x10000000
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}
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if { [info exists FLASH_SIZE] } {
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set _FLASH_SIZE $FLASH_SIZE
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} else {
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set _FLASH_SIZE 0x10000
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}
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if { [info exists FLC_BASE] } {
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set _FLC_BASE $FLC_BASE
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} else {
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set _FLC_BASE 0x40029000
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}
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if { [info exists FLASH_SECTOR] } {
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set _FLASH_SECTOR $FLASH_SECTOR
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} else {
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set _FLASH_SECTOR 0x2000
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}
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if { [info exists FLASH_CLK] } {
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set _FLASH_CLK $FLASH_CLK
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} else {
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set _FLASH_CLK 96
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}
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# OPTIONS_128 0x01 /* Perform 128 bit flash writes */
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# OPTIONS_ENC 0x02 /* Encrypt the flash contents */
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# OPTIONS_AUTH 0x04 /* Authenticate the flash contents */
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# OPTIONS_COUNT 0x08 /* Add counter values to authentication */
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# OPTIONS_INTER 0x10 /* Interleave the authentication and count values*/
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# OPTIONS_RELATIVE_XOR 0x20 /* Only XOR the offset of the address when encrypting */
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# OPTIONS_KEYSIZE 0x40 /* Use a 256 bit KEY */
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if { [info exists FLASH_OPTIONS] } {
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set _FLASH_OPTIONS $FLASH_OPTIONS
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} else {
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set _FLASH_OPTIONS 0
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}
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flash bank $_CHIPNAME.flash max32xxx $_FLASH_BASE $_FLASH_SIZE 0 0 $_CHIPNAME.cpu \
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$_FLC_BASE $_FLASH_SECTOR $_FLASH_CLK $_FLASH_OPTIONS
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# call allow_low_pwr_dbg to set this to 1
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set ALLOW_LOW_PWR_DBG 0
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proc allow_low_pwr_dbg {} {
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global ALLOW_LOW_PWR_DBG
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# set our low-power debug flag
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set ALLOW_LOW_PWR_DBG 1
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}
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# enable debug in case of low-power mode
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proc enable_debug {} {
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set DBGKEY 0xA05F0000
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set C_DEBUGEN 0x00000001
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set C_HALT 0x00000002
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echo "Enable debug to connect in low-power mode"
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# enable debug
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mww 0xE000EDF0 [expr {$DBGKEY | $C_HALT | $C_DEBUGEN}]
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# allow for time waking up
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sleep 500
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}
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$_CHIPNAME.cpu configure -event reset-deassert-post {
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global ALLOW_LOW_PWR_DBG
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if { $ALLOW_LOW_PWR_DBG == 1 } {
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enable_debug
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}
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}
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